A High-Speed 128-kb MRAM Core for Future Universal Memory Applications

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 4, 2004, Pages 678-683

  DeBrosse, John ^a   Gogl, Dietmar ^b   Bette, Alexander ^b   Hoenigschmid, Heinz ^b   Robertazzi, Raphael ^c   Arndt, Christian ^b   Braun, Daniel ^b   Casarotto, D ^b   Havreluk, R ^c   Lammers, Stefan ^b   Obermaier, Werner ^b   Reohr, William R ^a   Viehmann, H ^b   Gallagher, William J ^c   Müller, Gerhard ^b  

^a IBM MICROELECTRONICS   (United States)

^b INFINEON TECHNOLOGIES   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

1T1MTJ; Access time; MRAM; Reference cell; Symmetrical sensing; Universal memory

Indexed keywords

ACCESS TIME; REFERENCE CELLS; UNIVERSAL MEMORY;

ELECTRIC LOADS; ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; ELECTRON TUNNELING; EXTRAPOLATION; LOGIC DESIGN; METALLIZING; MICROPROCESSOR CHIPS;

RANDOM ACCESS STORAGE;

EID: 10044273066     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.825251     Document Type: Article

References (4)

1. W. Reohr et al., "Memories of tomorrow," IEEE Circuits Devices Mag., vol. 18, pp. 17-27, Sept. 2002.
2. M. Durlam et al., "A low power 1 Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects," in Symp. VLSI Circuits Dig. Tech. Papers, 2002, pp. 158-161.
3. H. Jeong et al., "Fully integrated 64 kb MRAM with novel reference cell scheme," in Proc. IEDM, 2002, pp. 551-554.
4. M. Motoyoshi et al., "High performance MRAM technology with an improved magnetic tunnel junction material," in Symp. VLSI Circuits Dig. Tech. Papers, 2002, pp. 212-213.