ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2011, Pages 411-418

  Khan, Omer ^a,b   Hoffmann, Henry ^b   Lis, Mieszko ^b   Hijaz, Farrukh ^a   Agarwal, Anant ^b   Devadas, Srinivas ^b  

^a UNIVERSITY OF MASSACHUSETTS LOWELL   (United States)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTICAL MODEL; CACHE COHERENCE; COHERENCE PROTOCOL; LOWER ENERGIES; MULTI-CORES; OFF-CHIP; SEAMLESS TRANSITION; SHARED CACHE;

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; ENERGY UTILIZATION; MATHEMATICAL MODELS;

NETWORK ARCHITECTURE;

EID: 83455210135     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2011.6081431     Document Type: Conference Paper

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