Improving the efficiency of static compaction based on chronological order enumeration of test sequences [logic testing]

Proceedings of the Asian Test Symposium

Volumn 2002-January, Issue , 2002, Pages 61-66

  Pomeranz, I ^a   Reddy, S M ^b  

^a PURDUE UNIVERSITY   (United States)

^b UNIVERSITY OF IOWA   (United States)

Author keywords

Automatic test pattern generation; Benchmark testing; Circuit faults; Circuit testing; Cities and towns; Compaction; Computational complexity; Performance evaluation; Sequential analysis; Sequential circuits

Indexed keywords

BENCHMARKING; COMPACTION; COMPUTATIONAL COMPLEXITY; EFFICIENCY; ELECTRIC NETWORK ANALYSIS; RESTORATION; SEQUENTIAL CIRCUITS; SWITCHING CIRCUITS;

BENCHMARK TESTING; CIRCUIT FAULTS; CIRCUIT TESTING; CITIES AND TOWNS; PERFORMANCE EVALUATION; SEQUENTIAL ANALYSIS;

AUTOMATIC TEST PATTERN GENERATION;

EID: 8344259700     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ATS.2002.1181686     Document Type: Conference Paper

References (12)

1. I. Pomeranz and S. M. Reddy, "On Static Compaction of Test Sequences for Synchronous Sequential Circuits", DAC-96, pp. 215-220.
2. I. Pomeranz and S. M. Reddy, "Vector Restoration Based Static Compaction of Test Sequences for Synchronous Sequential Circuits", ICCD-97, pp. 360-365.
3. M. S. Hsiao, E. M. Rudnick and J. H. Patel, "Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors", VTS-97, pp. 188-195.
4. M. S. Hsiao and S. T. Chakradhar, "State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits", DATE-98, pp. 577-582.
5. R. Guo, I. Pomeranz and S. M. Reddy, "Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration", DATE-98, pp. 583-587.
6. S. K. Bommu, S. T. Chakradhar and K. B. Doreswamy, "Static Test Sequence Compaction based on Segment Reordering and Accelerated Vector Restoration", ITC-98, pp. 954-961.
7. S. K. Bommu, S. T. Chakradhar and K. B. Doreswamy, "Static Compaction Using Overlapped Restoration and Segment Pruning", ICCAD-98, pp. 140-146.
8. R. Guo, I. Pomeranz and S. M. Reddy, "On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits", ATS-98, pp. 467-471.
9. R. Guo, I. Pomeranz and S. M. Reddy, "On Improving Static Test Compaction for Sequential Circuits", VLSI Design-01, pp. 111-116.
10. I. Pomeranz and S. M. Reddy, "An Approach for Improving the Levels of Compaction Achieved by Vector Omission", ICCAD-99, pp. 463-466.
11. M. S. Hsiao, E. M. Rudnick, and J. H. Patel, "Sequential Circuit Test Generation Using Dynamic State Traversal", ED&TC-97, pp. 22-28.
12. R. Guo, S. M. Reddy and I. Pomeranz, "PROPTEST: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction", DAC-99, pp. 653-659.