On speeding-up vector restoration based static compaction of test sequences for sequential circuits

Proceedings of the Asian Test Symposium

Volumn , Issue , 1998, Pages 467-471

  Guo, Ruifeng ^a   Pomeranz, Irith ^a   Reddy, Sudhakar M ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

VECTOR RESTORATION TECHNIQUES;

ALGORITHMS; INTEGRATED CIRCUIT TESTING; VECTORS;

SEQUENTIAL CIRCUITS;

EID: 0032305509     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. B. So, "Time Efficient Automatic Test Pattern Generation Systems", Ph.D thesis, EE dept, Univ. of Wisconsin at Madison, 1994
2. T.M. Niermann, R.K. Roy, J.H. Patel, and J.A. Abraham, "Test Compaction for Sequential Circuits,", IEEE Trans. Computer-Aided Design, vol. 11, no.2, Feb. 1992, pp. 260-267.
3. I. Pomeranz and S.M. Reddy, "On Static Compaction of Test Sequences for Synchronous Sequential Circuits", In Proc. 33rd Design Automation Conf., June 1996, pp. 215-220
4. M.S. Hsiao, E.M. Rudnick and J.H. Patel, "Fast Algorithm for Static Compaction of Sequential Circuit Test Vectors", in Proc. VLSI Test Symp., April 1997, pp. 188-195
5. I. Pomeranz and S.M. Reddy, "Vector Restoration Based Static Compaction of Test Sequence for Synchronous Sequential Circuits",in Proc. Intl. Conf. on Computer Design, Oct. 1997, pp.360-365
6. F. Corno. P. Prinetto, M. Rebaudengo and M. Conza Reorda, "New Static Compaction of Sequential Circuit Test Vectors", in Proc. VLSI Test Symp., April 1997, pp. 188-195
7. R. Guo, I. Pomeranz and S.M. Reddy, "Procedures for Static Compaction of Test Sequences for synchronous Sequential Circuits", in Proc. Eur op. Design Automation and Test Conf., Feb. 1998, pp. 583-587
8. M.S. Hsiao and S.T. Chakradhar, "State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits," Proc. Europ. Design Automation and Test Conf., Feb. 1998, pp. 572-576.
9. H.K. Lee and D.S. Ha, "HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits", in Proc. 1992 Design Automation Conf., June 1992, pp. 336-340
10. H.K. Lee and D.S. Ha, "New Technique for Improving Parallel Fault Simulation in Synchronous Sequential Circuits", In Proc. 1993 Intl. Conf. on Computer-Aided Design, Oct. 1993, pp. 10-17
11. M.S. Hsiao, E.M. Rudnick and J.H. Patel, "Sequential Circuit Test Generation Using Dynamic State Traversal" in Proc. 1996 Europ. Design & Test Conf. March 1996, pp. 22-28