On improving static test compaction for sequential circuits

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2001, Pages 111-116

  Guo, R ^a   Pomeranz, I ^a   Reddy, S M ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; PARALLEL ALGORITHMS; PATTERN MATCHING; VECTORS; VLSI CIRCUITS;

REVERSE ORDER RESTORATION (ROR); TEST SEQUENCES;

SEQUENTIAL CIRCUITS;

EID: 0035010247     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)