Effectively sharing a cache among threads

Annual ACM Symposium on Parallel Algorithms and Architectures

Volumn 16, Issue , 2004, Pages 235-244

  Blelloch, Guy E ^a   Gibbons, Phillip B ^b  

^a CARNEGIE MELLON UNIVERSITY   (United States)

^b INTEL RESEARCH   (United States)

Author keywords

Chip multiprocessors; Multithreaded architectures; Scheduling algorithms; Shared cache

Indexed keywords

COMPUTATION THEORY; LOGIC DESIGN; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; PROGRAM PROCESSORS; VIRTUAL STORAGE;

CHIP MULTIPROCESSORS; MULTITHREAD ARCHITECTURE; SCHEDULING ALGORITHMS; SHARED CACHE;

CACHE MEMORY;

EID: 8344240379     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1007912.1007948     Document Type: Conference Paper

References (31)

1. U. A. Acar, G. E. Blelloch, and R. D. Blumofe. The data locality of work stealing. Theory of Computing Systems, 35(3):321-347, 2002.
2. A. Agarwal, M. Horowitz, and J. L. Hennessy. An analytical cache model. A CM Trans. on Computer Systems, 7(2): 184~215, 1989.
3. L. Arge, M. A. Bender, E. D. Demaine, B. Holland-Minkley, and J. I. Munro. Cache-oblivious priority queue and graph algorithm applications. In Proc. 34th ACM Symp. on Theory of Computing (STOC), pages 268-276, May 2002.
4. L. A. Barroso, K. Gharachorloo, R. McNamara, A. Nowatzyk, S. Qadeer, B. Sano, S. Smith, R. Stets, and B. Verghese. Piranha: A scalable architecture based on single-chip multiprocessing. In Proc. 27th ACM International Symp. on Computer Architecture (ISCA), pages 282-293, June 2000.
5. R. D. Barve, E. F. Grove, and J. S. Vitter. Application-controlled paging for a shared cache. SIAM Journal on Computing, 29(4):1290-1303, 2000.
6. L. A. Belady. A study of replacment algorithms for virtual storage computers. IBM Systems Journal, 5(2):78-101, 1966.
7. G. E. Blelloch, P. B. Gibbons, and Y. Matias. Provably efficient scheduling for languages with fine-grained parallelism. Journal of the ACM, 46(2):281-321, 1999.
8. G. E. Blelloch, P. B. Gibbons, Y. Matias, and G. J. Narlikar. Space-efficient scheduling of parallelism with synchronization variables. In Proc. 9th ACM Symp. on Parallel Algorithms and Architectures (SPAA), pages 12-23, June 1997.
9. R. D. Blumofe, M. Frigo, C. F. Joerg, C. E. Leiserson, and K. H. Randall. An analysis of dag-consistent distributed shared-memory algorithms. In Proc. 8th ACM Symp. on Parallel Algorithms and Architectures (SPAA), pages 297-308, June 1996.
10. R. D. Blumofe and C. E. Leiserson. Scheduling multithreaded computations by work stealing. Journal of the ACM, 46(5):720-748, 1999.
11. Y.-Y. Chen, J.-K. Peir, and C.-T. King. Performance of shared caches on multithreaded architectures. Journal of Information Science and Engineering, 14(2):499-514, 1998.
12. P. Fatourou. Low-contention depth-first scheduling of parallel computations with write-once synchronization variables. In Proc. 13th ACM Symp. on Parallel Algorithms and Architectures (SPAA), pages 189-198, July 2001.
13. M. Frigo, C. E. Leiserson, H. Prokop, and S. Ramachandran. Cache-oblivious algorithms. In Proc. 40th IEEE Symp. on Foundations of Computer Science (FOCS), pages 285-298, Oct. 1999.
14. L. Hammond, B. A. Hubbert, M. Siu, M. K. Prabhu, M. Chen, and K. Olukotun. The Stanford Hydra CMP. IEEE Micro, 20(2):71-84, 2000.
15. L. Hammond, B. Nayfeh, and K. Olukotun. A single-chip multiprocessor. IEEE Computer, 30(9):79-85, 1997.
16. S. Irani. Competitive analysis of paging. In Online Algorithms. Springer, 1998. LNCS, 1442:52-73.
17. N. P. Jouppi. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. In Proc. 17th ACM International Symp. on Computer Architecture (ISCA), pages 364-373, May 1990.
18. R. Kalla, B. Sinharoy, and J. Tendler. Simultaneous multi-threading implementation in POWER5. In 15th IEEE Hot Chips, Aug. 2003.
19. D. T. Marr, F. Binns, D. L. Hill, G. Hinton, D. A. Koufaty, J. A. Miller, and M. Upton. Hyper-threading technology architecture and microarchitecture, white paper. Intel Technical Journal, 6(1), Feb. 2002.
20. D. Naishlos, J. Nuzman, C.-W. Tseng, and U. Vishkin. Towards a first vertical prototyping of an extremely fine-grained parallel programming approach. In Proc. 13th ACM Symp. on Parallel Algorithms and Architectures (SPAA), pages 93-102, July 2001.
21. G. J. Narlikar. Scheduling threads for low space requirement and good locality. Theory of Computing Systems, 35(2):151-187, 2002.
22. G. J. Narlikar and G. E. Blelloch. Space-efficient scheduling of nested parallelism. ACM Trans. on Programming Languages and Systems, 21(1):138-173, 1999.
23. R. H. Saavedra-Barrera, D. E. Culler, and T. von Eicken. Analysis of multithreaded architectures for parallel computing. In Proc. 2nd ACM Symp. on Parallel Algorithms and Architectures (SPAA), pages 169-178, July 1990.
24. D. D. Sleator and R. E. Tarjan. Amortized efficiency of list update and paging rules. Communications of the ACM, 28(2):202-208, 1985.
25. G. E. Suh, S. Devadas, and L. Rudolph. Analytical cache models with application to cache partitioning. In Proc. 2001 ACM International Conference on Supercomputing, pages 1-12, June 2001.
26. G. E. Suh, L. Rudolph, and S. Devadas. Dynamic partitioning of shared cache memory. Journal of Supercomputing, 28(1):7-26, 2004.
27. J. M. Tendler, S. Dodson, S. Fields, H. Le, and B. Sinharoy. Power4 system microarchitecture, technical white paper. Technical Report 20, IBM Server Group, Oct. 2001.
28. D. Thibaut and H. S. Stone. Footprints in the cache. ACM Trans. on Computer Systems, 5(4):305-329, 1987.
29. D. Thibaut and H. S. Stone. Improving disk cache hit-ratios through cache partitioning. IEEE Transactions on Computers, 41(6):665-676, 1992.
30. M. Tremblay, J. Chan, S. Chaudhry, A. W. Conigliaro, and S. S. Tse. The MAJC architecture: A synthesis of parallelism and scalability. IEEE Micro, 20(6): 12-25, 2000.
31. D. M. Tullsen, S. J. Eggers, and H. M. Levy. Simultaneous multithreading: Maximizing on-chip parallelism. In Proc. 22nd ACM International Symp. on Computer Architecture (ISCA), pages 392-403, June 1995.