Performance of shared caches on multithreaded architectures

Journal of Information Science and Engineering

Volumn 14, Issue 2, 1998, Pages 499-514

  Chen, Yunn Yen ^a,c,d   Peir, Jih Kwon ^b   King, Chung Ta ^c  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^b University of Florida   (United States)

^c NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^d UNIVERSITY OF FLORIDA   (United States)

Author keywords

Cache system; Computer architecture; Multithreaded execution; Performance evaluation; Scheduling

Indexed keywords

ASSOCIATIVE STORAGE; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; COMPUTER WORKSTATIONS; FAULT TOLERANT COMPUTER SYSTEMS; MULTIPROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS); STORAGE ALLOCATION (COMPUTER);

MULTITHREADED ARCHITECTURES; TRACE DRIVEN SIMULATIONS;

BUFFER STORAGE;

EID: 0032095557     PISSN: 10162364     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (22)

1. R. Alverson, D. Callahan, D. Cummings, B. Koblenz, A. Porterfield and B. Smith, "The tera computer system," in Proceedings of international Coference on SuperComputing, 1990, pp. 1-6.
2. A. Argawal, "Performance tradeoffs in multithreaded processors," IEEE Transactions on Parallel and Distributed Systems, Vol. 3, No. 5, 1992, pp. 525-539.
3. A. Argawal, D. Chaiken, K. Johnson, D. Kranz, J. Kubiatowicz, K. Kurihara, B.H. Lim and G. Maa, D. Nussbaum, "The MIT alewife machine: A large-scale distributed-memory multiprocessor," in Proceedings of Workshop of Multithreaded Computers, Supercomputing '91, 1991, pp. 239-262.
4. Arvind, D.E. Culler, "The tagged token dataflow architecture," Technical Report, MIT Laboratory for Computer Science, 1984.
5. Y.Y. Chen et. al., "MITFAB: A monitoring and interfacing tracing facility architecture benchmarking," Technical Report, Department of Computer Science, University of Florida, 1994.
6. C. Conti, "Concepts for buffer storage," IEEE Computer Group News, Vol. 2, No. 8, 1969, pp. 9-13.
7. W. Dally, L. Chao, A. Chien, S. Hassoun, W. Horwat, J. Kaplan, P. Song, B. Totty and S. Wills, "Architecture of a message-driven processor," in Proceedings of the 14th Annual International Symposium on Computer Architecture, 1987, pp. 189-196.
8. J.B. Dennis, "Data flow supercomputers," IEEE Computer, Vol. 13, No. 11, 1980, pp. 48-56.
9. R.A. Halstread and T. Fujita, "A multithreaded processor architecture for parallel symbolic computing," in Proceedings of 15th International Symposium on Computer Architecture, 1988, pp. 443-451.
10. Peter Hsu, Shadow User Manual, Sun Microsystems, 1992.
11. Kai Hwang, Advanced Computer Architecture - Parallelism, Scalability, Programmability, McGraw-Hill, 1993.
12. R.A. Iannucci, "Toward a dataflow/von neumann hybrid architecture," in Proceedings of 15th International Symposium on Computer Architecture, 1988, pp. 131-140.
13. R. Iannucci, A. Agarwal, Bill Dally, G. Papadopoulos and B. Smith, "Architectural and implementation issues for multiprocessing," Computer Architecture News, Vol. 22, No. 1, 1994, pp. 3-18.
14. D. Kroft, "Lookup-free instruction fetch/prefetch cache organization," in Proceedings of 8th International Symposium on Computer Architecture, 1981, pp. 81-87.
15. R.S. Nikhil and Arvind, "Can dataflow subsume von neumann computing?" in Proceedings 16th Annual International Symposium on Computer Architecture, 1989, pp. 262-272.
16. R.S. Nikhil, G.M. Papadopoulos and Arvind, "*T: A multithreaded massively parallel architecture," in Proceedings of 19th International Symposium on Computer Architecture, 1988, pp. 156-167.
17. W.H. Press, B.P. Flannery, S.A. Teukolsky, and W.T. Vetterling, Numerical Recipes: The Art of Scientific Computing, Cambridge University Press, 1985.
18. R. Saavedra-Barrera, D.E. Culler, and T. Von Eiken, "Analysis of multithreaded architectures for parallel computing," in Proceedings of 2nd ACM Symposium on Parallel Algorithms and Architectures, 1990, pp. 169-178.
19. A.J. Smith, "Cache memories," ACM Computing Surveys, Vol. 14, No. 3, 1992, pp. 473-530.
20. R.J. Smith, "Architecture and applications of the HEP multiprocessor computer system," Real-Time Signal Processing IV, Vol. 298, 1981, pp. 241-248.
21. P. Spee, W.F. Wong and E. Goto, "Effects of multiple instruction stream execution on cache performance," International Journal of High Speed Computing, Vol. 3, No. 2, 1991, pp. 135-155.
22. J.E. Thornton, Design of a Computer: The Control Data 6600, Scott, Foresman, Glenview, IL, 1970.