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Volumn 37, Issue 6, 2011, Pages 958-972
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Design and evaluation of low latency interconnection networks for real-time many-core embedded systems
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Author keywords
[No Author keywords available]
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Indexed keywords
AVERAGE DISTANCE;
BISECTION BANDWIDTH;
CRITICAL LINKS;
LOW DIAMETERS;
LOW LATENCY;
LOW-LATENCY NETWORKS;
MANY-CORE;
ON-CHIP INTERCONNECTION NETWORK;
REAL TIME;
SHARING NETWORK;
WORST CASE;
ASYNCHRONOUS SEQUENTIAL LOGIC;
COSTS;
EMBEDDED SYSTEMS;
INTERCONNECTION NETWORKS;
ROUTERS;
WIRELESS SENSOR NETWORKS;
REAL TIME SYSTEMS;
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EID: 82655181790
PISSN: 00457906
EISSN: None
Source Type: Journal
DOI: 10.1016/j.compeleceng.2011.08.008 Document Type: Article |
Times cited : (7)
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References (27)
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