Numerical analysis of slow current transients and power compression in GaAs FETs

IEEE Transactions on Electron Devices

Volumn 51, Issue 11, 2004, Pages 1760-1764

  Kazami, Yusuke ^a   Kasai, Daisuke ^a   Horio, Kazushige ^a  

^a SHIBAURA INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; IMPACT IONIZATION; NUMERICAL ANALYSIS; POISSON EQUATION; SEMICONDUCTING GALLIUM ARSENIDE; SEMICONDUCTOR DEVICE MODELS; SUBSTRATES; TRANSIENTS;

DRAIN LAG; GALLIUM ARSENIDE MESFET; GATE LAG; POWER COMPRESSION; QUASI PULSED CURRENT VOLTAGE CURVES; SLOW CURRENT TRANSIENTS; SUBSTRATE TRAP; SURFACE STATE;

MESFET DEVICES;

EID: 8144230246     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.837383     Document Type: Article

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