Compact physical models for multilevel interconnect crosstalk in gigascale integration (GSI)

IEEE Transactions on Electron Devices

Volumn 51, Issue 11, 2004, Pages 1902-1912

  Naeemi, Azad ^a   Davis, Jeffrey Alan ^a   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CROSSTALK; ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; INDUCTANCE; INTEGRAL EQUATIONS; OPTIMIZATION; SEMICONDUCTOR DEVICE MODELS; SPURIOUS SIGNAL NOISE; TRANSMISSION LINE THEORY;

AGGRESSORS; GIGASCALE INTEGRATION CHIP; INTERCONNECTS; SYSTEM OPTIMIZATION;

VLSI CIRCUITS;

EID: 8144224616     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.837379     Document Type: Article

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