Symbolic design space exploration for multi-mode reconfigurable systems

Embedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 9th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS'11

Volumn , Issue , 2011, Pages 129-138

  Wildermann, Stefan ^a   Reimann, Felix ^a   Ziener, Daniel ^a   Teich, Jürgen ^a  

^a UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL MODELS; DESIGN SPACE EXPLORATION; EXISTING SYSTEMS; MULTI OBJECTIVE EVOLUTIONARY ALGORITHMS; MULTIMODE SYSTEM; MULTIMODES; ON CHIP COMMUNICATION; OPERATIONAL MODES; OPTIMIZATION TECHNIQUES; PARTIAL RECONFIGURATION; PARTIALLY RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE MODULE; RECONFIGURABLE SYSTEMS; RECONFIGURABLE TECHNOLOGIES; RUNTIMES; SAT SOLVERS; STATE MACHINE; STATE-OF-THE-ART TECHNOLOGY; SYSTEM SPECIFICATION; TEMPORAL BEHAVIOR; TEST CASE; UNIFIED SYSTEM;

ENCODING (SYMBOLS); EVOLUTIONARY ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE PROCESSING; MULTIOBJECTIVE OPTIMIZATION; RECONFIGURABLE HARDWARE; SPACE RESEARCH; SPECIFICATIONS; STRUCTURAL DESIGN;

EMBEDDED SYSTEMS;

EID: 81355132242     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2039370.2039393     Document Type: Conference Paper

References (21)

1. M. Schmitz, B. Al-Hashimi, and P. Eles, "Cosynthesis of energy-effcient multimode embedded systems with consideration of mode-execution probabilities, " IEEE TCAD, vol. 24, no. 2, pp. 153{169, 2005.
2. S. Wildermann, A. Oetken, J. Teich, and Z. Salcic, "Self-organizing computer vision for robust object tracking in smart cameras, " in Proc. of ATC, 2010, pp. 1{16.
3. R. Müller and J. Teubner, "FPGA: what's in it for a database?" in SIGMOD, 2009, pp. 999{1004.
4. P. Lysaght, B. Blodget, J. Mason, J. Young, and B. Bridgford, "Invited paper: Enhanced architectures, design methodologies and CAD tools for dynamic reconfiguration of Xilinx FPGAs, " in Proc. of FPL, 2006, pp. 1{6.
5. J. Hagemeyer, B. Kettelhoit, M. Koester, and M. Porrmann, "INDRA { integrated design ow for recon-gurable architectures, " in Proc. of DATE, 2007.
6. D. Koch, C. Beckhoff, and J. Teich, "ReCoBus-Builder - a Novel Tool and Technique to Build Statically and Dynamically Reconfigurable Systems for FPGAs, " in Proc. of FPL, Heidelberg, Germany, Sep. 2008, pp. 119{124.
7. B. Kienhuis, E. Deprettere, K. Vissers, and P. Van Der Wolf, "An approach for quantitative analysis of application-speci-c dataow architectures, " in Proc. of ASAP, 1997, pp. 338{349.
8. L. Huang and Q. Xu, "Energy-effcient task allocation and scheduling for multi-mode MPSoCs under lifetime reliability constraint, " in Proc. of DATE, 2010, pp. 1584{1589.
9. M. Lukasiewycz, M. Glaß, C. Haubelt, and J. Teich, "Effcient symbolic multi-objective design space exploration, " in Proc. of ASP-DAC, 2008, pp. 691{696.
10. D. GÖohringer, M. Hübner, M. Benz, and J. Becker, "A design methodology for application partitioning and architecture development of reconfigurable multiprocessor systems-on-chip, " in Proc. of FCCM, 2010, pp. 259{262.
11. S. Fekete, E. Köhler, and J. Teich, "Optimal FPGA module placement with temporal precedence constraints, " in Proc. of DATE, 2001, pp. 658{667.
12. K. Danne and S. Stühmeier, "Off-line placement of tasks onto reconfigurable hardware considering geometrical task variants, " in From Specidication to Embedded Systems Application. Springer, 2005, pp. 311{311.
13. J. Hagemeyer, B. Kettelhoit, M. Koester, and M. Porrmann, "Design of homogeneous communication infrastructures for partially reconfigurable FPGAs, " in Proc. of ERSA, 2007, pp. 238{247.
14. D. Koch, C. Haubelt, and J. Teich, "E-cient recon-gurable on-chip buses for FPGAs, " in Proc of FCCM, 2008, 287{290
15. H. ElGindy, H. Schroder, A. Spray, A. Somani, and H. Schmeck, "RMB - A reconfigurable multiple bus network, " in Proc. of HPCA, 1996, pp. 108{117.
16. T. Blickle, J. Teich, and L. Thiele, "System-level synthesis using evolutionary algorithms, " Design Automation for Embedded Systems, vol. 3, pp. 23{58, 1998.
17. D. Koch, C. Beckhoff, and J. Teich, "Minimizing internal fragmentation by fine-grained two-dimensional module placement for runtime reconfigurable systems, " in Proc. of FCCM, 2009, pp. 251{254.
18. M. Koester, W. Luk, J. Hagemeyer, M. Porrmann, and U. Ruckert, "Design optimizations for tiled partially recon-gurable systems, " IEEE TVLSI, no. 99, pp. 1{14, 2010.
19. M. Lukasiewycz, M. Streubühr, M. Glaß, C. Haubelt, and J. Teich, "Combined system synthesis and communication architecture exploration for MPSoCs, " in Proc. of DATE, 2009, pp. 472{477.
20. A. Oetken, S. Wildermann, J. Teich, and D. Koch, "A bus-based SoC architecture for exible module placement on reconfigurable FPGAs, " in Proc. of FPL, 2010, pp. 234{239.
21. M. Lukasiewycz, M. Glaß, F. Reimann, and J. Teich, "Opt4J - a modular framework for meta-heuristic optimization, " in Proc. of GECCO, 2011.