Minimizing internal fragmentation by fine-grained two-dimensional module placement for runtime reconfigurable systems

Proceedings - IEEE Symposium on Field Programmable Custom Computing Machines, FCCM 2009

Volumn , Issue , 2009, Pages 251-254

  Koch, Dirk ^a   Beckhoff, Christian ^a   Teich, Jürgen ^a  

^a UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK RAMS; COMMUNICATION ARCHITECTURES; MODULE PLACEMENT; RE-CONFIGURABLE; RECONFIGURABLE MODULE; RUN-TIME RECONFIGURABLE; TWO DIMENSIONAL COMMUNICATION;

COMPUTERS;

TWO DIMENSIONAL;

EID: 74349114560     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2009.40     Document Type: Conference Paper

References (6)

1. J. Hagemeyer, B. Kettelhoit, M. Kster, and M. Porrmann. Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs. In Proc. of ERSA'07, Las Vegas, USA, June 2007.
2. D. Koch, C. Beckhoff, and J. Teich. ReCoBus-Builder a Novel Tool and Technique to Build Statically and Dynamically Reconfigurable Systems for FPGAs. In Proc. of FPL 08, pages 119-124, Heidelberg, Germany, Sept. 2008.
3. D. Koch, C. Beckhoff, and J. Teich. A Communication Architecture for Complex Runtime Reconfigurable Systems and its Implementation on Spartan-3 FPGAs. In Proc. FPGA 2009, pages 253-256, Monterey, California, USA, Feb. 2009.
4. D. Koch, C. Haubelt, and J. Teich. Efficient Reconfigurable On-Chip Buses for FPGAs. In Proc. FCCM 2008, pages 287-290, Palo Alto, CA, USA, Apr. 2008.
5. T. Pionteck, et al. Communication Architectures for Dynamically Reconfigurable FPGA Designs. In Proc. IPDPS'07, Long Beach, California, USA, 2007.
6. M. Ullmann, M. Hübner, and J. Becker. An FPGA Run-Time System for Dynamical On-Demand Reconfiguration. In Proc. IPDPS'04, Santa Fe, New Mexico, Apr. 2004.