Off-line placement of tasks onto reconfigurable hardware considering geometrical task variants

IFIP Advances in Information and Communication Technology

Volumn 184, Issue , 2005, Pages 311-320

  Danne, Klaus ^a   Stühmeier, Sven ^a  

^a UNIVERSITY OF PADERBORN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; EMBEDDED SYSTEMS; HEURISTIC METHODS; HARDWARE; RECONFIGURABLE HARDWARE;

FLOOR-PLANNING; LINE PLACEMENT; PACKING PROBLEMS; RECONFIGURABLE HARDWARE DEVICES; HARDWARE DEVICES;

RECONFIGURABLE HARDWARE; HEURISTIC METHODS;

EID: 84880351246     PISSN: 18684238     EISSN: None     Source Type: Book Series    
DOI: 10.1007/11523277_30     Document Type: Article

References (6)

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3. S. P. Fekete, E. Köhler, and J. Teich. Optimale FPGA module placement with temporal precedence constraints. In Proc. DATE 2001, Design, Automation and Test an Europe, pages 65&665, Munich, Germany, March 13-16 2001. IEEE Computer Society Press.
4. K. Bazargan, R. Kastner, and M. Sarrafzadeh. Fast template placement for reconfigurable computing systems. IEEE Design and Test of Computers, pages 68-83, March 2000.
5. Christophe Bobda. Synthesis of Datafiow Graphs for Reconfigumble Systems using Tempoml Partitioning and Tempoml Placement. Dissertation, Universität Paderborn, Heinz Nixdorf Institut, Entwurf Paralleler Systeme, 2003. Euro 35,-
6. Thomas Lengauer. Combinatorial Algorithms for Integrated Circuit Layout. John ISBN 3-935433-37-9. Wiley, 1990.