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Volumn , Issue , 2008, Pages 287-290

Efficient reconfigurable on-chip buses for fpgas

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTERS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 60349093213     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FCCM.2008.33     Document Type: Conference Paper
Times cited : (21)

References (8)
  • 1
    • 33751416365 scopus 로고    scopus 로고
    • Rapid Prototyping Design Acceleration Using a Novel Merging Methodology for Partial Configuration Streams of Xilinx Virtex-II FPGAs
    • Los Alamitos, CA, USA
    • C. Bieser and K.-D. Mueller-Glaser. Rapid Prototyping Design Acceleration Using a Novel Merging Methodology for Partial Configuration Streams of Xilinx Virtex-II FPGAs. In 17th IEEE Int. Workshop on Rapid System Prototyping, pages 193-199, Los Alamitos, CA, USA, 2006.
    • (2006) 17th IEEE Int. Workshop on Rapid System Prototyping , pp. 193-199
    • Bieser, C.1    Mueller-Glaser, K.-D.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.