Fast ripple-carry adders in standard-cell CMOS VLSI

Proceedings - Symposium on Computer Arithmetic

Volumn , Issue , 2011, Pages 103-111

  Burgess, Neil ^a  

^a ARM Inc   (United States)

Author keywords

Adders; CMOS VLSI; Ling

Indexed keywords

ADDITION TECHNIQUE; CMOS VLSI; CRITICAL PATHS; DSP ALGORITHM; FLOATING POINT UNITS; LING; PREFIX ADDERS; RIPPLE CARRY ADDERS; STANDARD-CELL; WORD LENGTH;

INTEGRATED CIRCUIT TESTING; VLSI CIRCUITS;

ADDERS;

EID: 80055042996     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARITH.2011.23     Document Type: Conference Paper

References (11)

1. th IEEE Computer Arithmetic Symposium, Adelaide, 1999, pp. 277 - 281
2. J-F. Lin, M-H. Sheu and Y-T Hwang, "Low-Power and Low-Complexity Full Adder Design for Wireless Base Band Application", Proc. IEEE Int. Conf. on Communications, Circuits and Systems, Guilin, China, 2006, Vol. 4, pp. 2337 - 2341
3. X. Zeng and P. Wang, "Design of low-power Complementary Pass-Transistor and ternary adder based on multi-valued switchsignal theory", Proc. 8th IEEE International Conference on ASIC, (ASICON '09), Changsha, China, 2009, pp. 851 - 854
4. R. Zimmermann and W. Fichtner, "Low-power logic styles: CMOS versus pass-transistor logic", IEEE J. Solid-State Circuits, Vol. 32, (July 1997), pp. 1079 - 1090
5. J. Grad and J.E. Stine, "New algorithms for carry propagation", Proc. 15th ACM Great Lakes symposium on VLSI, Chicago, 2005, pp. 396 - 399
6. S. Knowles, "Arithmetic processor design for the T9000 transputer", Proc. SPIE, Vol. 1566, San Diego, 1991, pp. 230 - 243.
7. H. Ling, "High-Speed Binary Adder", IBM J. Research & Dev., vol 25, p.156-166 (May 1981)
8. R. Jackson and S. Talwar, "High-Speed Binary Addition", Proc. 38th IEEE Asilomar Conference on Systems, Signals, and Computers, Asilomar, CA, 2005, 1350-1353
9. A. Vazquez and E. Antelo, "New insights on Ling adders", Proc. IEEE Int. Conf. on Application-Specific Systems, Architectures and Processors, Leuven, 2008 pp. 227 - 232
10. N. Weste and D. Harris, CMOS VLSI Design, 4/e, Addison-Wesley, 2010
11. N. Burgess, "New Models of Prefix Adder Topologies", J. VLSI Signal Processing Systems, Vol. 40, (June 2004), pp. 125 - 141.