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Volumn , Issue , 2008, Pages 227-232

New insights on ling adders

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION-SPECIFIC SYSTEMS; FLOATING-POINT UNITS; INTERNATIONAL CONFERENCES;

EID: 51649124965     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASAP.2008.4580183     Document Type: Conference Paper
Times cited : (5)

References (15)
  • 1
    • 0036644446 scopus 로고    scopus 로고
    • The Flagged Prefix Adder and its Applications in Integer Arithmetic
    • July
    • N. Burgess, "The Flagged Prefix Adder and its Applications in Integer Arithmetic", Journal of VLSI Signal Processing, vol. 31, no. 3, pp. 263-271, July 2002.
    • (2002) Journal of VLSI Signal Processing , vol.31 , Issue.3 , pp. 263-271
    • Burgess, N.1
  • 2
    • 14844366754 scopus 로고    scopus 로고
    • High-Speed Parallel-Prefix VLSI Ling Adders
    • Feb
    • G. Dimitrakopoulos and D. Nikolos, "High-Speed Parallel-Prefix VLSI Ling Adders", IEEE Trans. on Computers, vol. 54, no. 2, pp. 225-231, Feb. 2005.
    • (2005) IEEE Trans. on Computers , vol.54 , Issue.2 , pp. 225-231
    • Dimitrakopoulos, G.1    Nikolos, D.2
  • 3
    • 0024073321 scopus 로고
    • Variants of an Improved Carry-Lookahead Adder
    • Sep
    • R.W. Doran, "Variants of an Improved Carry-Lookahead Adder", IEEE Trans. on Computers, vol. 37, no. 9, pp. 1110-1113, Sep. 1988.
    • (1988) IEEE Trans. on Computers , vol.37 , Issue.9 , pp. 1110-1113
    • Doran, R.W.1
  • 8
    • 11944260934 scopus 로고    scopus 로고
    • A 4-GHz 300-mW 64-bit Integer Execution ALU with Dual Supply Voltages in 90-nm CMOS
    • Jan
    • S.K. Mathew et al., "A 4-GHz 300-mW 64-bit Integer Execution ALU with Dual Supply Voltages in 90-nm CMOS", IEEE Journal of Solid-State Circuits, vol. 40, no 1, pp. 44-51, Jan. 2005.
    • (2005) IEEE Journal of Solid-State Circuits , vol.40 , Issue.1 , pp. 44-51
    • Mathew, S.K.1
  • 9
    • 0030086663 scopus 로고    scopus 로고
    • A Sub-Nanosecond 0.5μm 64b Adder Design
    • Feb
    • S. Naffziger, "A Sub-Nanosecond 0.5μm 64b Adder Design", in Proc. IEEE Solid-State Circuits Conf., pp. 362-363, Feb. 1996.
    • (1996) Proc. IEEE Solid-State Circuits Conf , pp. 362-363
    • Naffziger, S.1
  • 10
    • 0001083804 scopus 로고
    • A Reduced-Area Scheme for Carry-Select Adders
    • Oct
    • A. Tyagi, "A Reduced-Area Scheme for Carry-Select Adders", IEEE Trans. on Computers, vol. C-42, no. 10, pp. 1163-1170, Oct. 1993.
    • (1993) IEEE Trans. on Computers , vol.C-42 , Issue.10 , pp. 1163-1170
    • Tyagi, A.1
  • 12
    • 0001138583 scopus 로고
    • High Speed Addition in CMOS
    • Dec
    • N. Quach and M. J. Flynn, "High Speed Addition in CMOS", IEEE Trans. on Computers, vol. 41, no. 12, pp. 1612-1615, Dec. 1992.
    • (1992) IEEE Trans. on Computers , vol.41 , Issue.12 , pp. 1612-1615
    • Quach, N.1    Flynn, M.J.2
  • 13
    • 0036098656 scopus 로고    scopus 로고
    • The Design of Hybrid Carry-Lookahed/Carry-Select Adders
    • Jan
    • Y. Wang, C. Pai, and X. Song, "The Design of Hybrid Carry-Lookahed/Carry-Select Adders", IEEE Trans. Circuits Syst. II, vol. 49, no. 1, pp. 16-24, Jan. 2002.
    • (2002) IEEE Trans. Circuits Syst. II , vol.49 , Issue.1 , pp. 16-24
    • Wang, Y.1    Pai, C.2    Song, X.3
  • 15
    • 84893788373 scopus 로고    scopus 로고
    • Power-Performance Optimal 64-Bit Carry-Lookahead Adders
    • Sep
    • R. Zlatanovici et al., "Power-Performance Optimal 64-Bit Carry-Lookahead Adders", in Proc. ESSCIRC 2003, pp. 321-324, Sep. 2003.
    • (2003) Proc. ESSCIRC , pp. 321-324
    • Zlatanovici, R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.