Design of low-power complementary pass-transistor and ternary adder based on multi-valued switch-signal theory

ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC

Volumn , Issue , 2009, Pages 851-854

  Zeng, Xiaopang ^a   Wang, Pengjun ^a,b  

^a NINGBO UNIVERSITY   (China)

^b FUDAN UNIVERSITY   (China)

Author keywords

Adder; CPL; Low power; Multiple value logic; Switch signal theory

Indexed keywords

CIRCUIT DELAYS; CIRCUIT STRUCTURES; COMPLEMENTARY PASS-TRANSISTOR LOGIC; FULL ADDERS; LEVEL DESIGN; LOGIC FUNCTIONS; LOW POWER; MULTIPLE-VALUE LOGIC; P-SPICE SIMULATION; RIPPLE CARRY ADDERS; SYMMETRY STRUCTURES; VALUE LOGIC; VLSI DESIGN;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DESIGN; ELECTRIC POWER SUPPLIES TO APPARATUS; SIGNAL THEORY; SPICE;

ADDERS;

EID: 77949343940     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASICON.2009.5351560     Document Type: Conference Paper

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