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Volumn 4, Issue , 2006, Pages 2337-2341

Low-power and low-complextly full adder design for wireless base band application

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; SYSTEMS ANALYSIS; THRESHOLD VOLTAGE; WIRELESS TELECOMMUNICATION SYSTEMS;

EID: 39749182680     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCCAS.2006.285145     Document Type: Conference Paper
Times cited : (3)

References (8)
  • 2
    • 0031189144 scopus 로고    scopus 로고
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    • R. Zimmermann and W. Fiehtner, "Low-power logic styles: CMOS versus pass- transistor logic," IEEE J. Solid-State Circuits, vol. 32. no.7, pp. 1079-1090, Jul. 1997.
    • (1997) IEEE J. Solid-State Circuits , vol.32 , Issue.7 , pp. 1079-1090
    • Zimmermann, R.1    Fiehtner, W.2
  • 3
    • 0026866556 scopus 로고
    • A new design of the CMOS full adder
    • May
    • N. Zhuang and H. Wu, "A new design of the CMOS full adder," IEEE J. of Solid state circuits, Vol. 27, pp.840-844, May 1992.
    • (1992) IEEE J. of Solid state circuits , vol.27 , pp. 840-844
    • Zhuang, N.1    Wu, H.2
  • 4
    • 0033730819 scopus 로고    scopus 로고
    • A Novel High-Performance CMOS 1-Bit Full Adder Cell
    • May
    • A. M. Shams and Magdy A. Bayoumi, "A Novel High-Performance CMOS 1-Bit Full Adder Cell, " IEEE Trans.On Ckt andSystems-II, Vol.47 No.5, May 2000.
    • (2000) IEEE Trans.On Ckt andSystems-II , vol.47 , Issue.5
    • Shams, A.M.1    Bayoumi, M.A.2
  • 5
    • 0028467137 scopus 로고
    • New efficient designs for XOR and XNOR functions on the transistor level
    • July
    • J.Wang, S. Fang, and W. Feng, "New efficient designs for XOR and XNOR functions on the transistor level," IEEE J. Solid-State Circuits, vol. 29, pp. 780-786, July 1994.
    • (1994) IEEE J. Solid-State Circuits , vol.29 , pp. 780-786
    • Wang, J.1    Fang, S.2    Feng, W.3
  • 6
    • 0033312440 scopus 로고    scopus 로고
    • A novel low-power energy recovery full adder cell
    • Feb
    • R. Shalem, E. John, and L. K. John, "A novel low-power energy recovery full adder cell," in Proc. Great Lakes Symp. VLSI, pp. 380-383, Feb. 1999.
    • (1999) Proc. Great Lakes Symp. VLSI , pp. 380-383
    • Shalem, R.1    John, E.2    John, L.K.3
  • 7
    • 0036103389 scopus 로고    scopus 로고
    • Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates
    • PP, Jan
    • H. T. Bui, Y. Wang, and Y. Jiang, "Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates," IEEE Trans. On Ckt and Systems II, Vol. 49 , no. 1, PP.25-30, Jan 2002.
    • (2002) IEEE Trans. On Ckt and Systems II , vol.49 , Issue.1 , pp. 25-30
    • Bui, H.T.1    Wang, Y.2    Jiang, Y.3
  • 8
    • 12744279044 scopus 로고    scopus 로고
    • A low power 10-transistor full adder cell for embedded architectures
    • Sydney ,Australia, pp, May
    • A. Fayed and M. Bayoumi, "A low power 10-transistor full adder cell for embedded architectures," IEEE Symposium of Circuits and Systems, Sydney ,Australia, pp.226-229, May 2001.
    • (2001) IEEE Symposium of Circuits and Systems , pp. 226-229
    • Fayed, A.1    Bayoumi, M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.