High speed binary addition

Conference Record - Asilomar Conference on Signals, Systems and Computers

Volumn 2, Issue , 2004, Pages 1350-1353

  Jackson, Robert ^a   Talwar, Sunil ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; FUNCTIONS; HIERARCHICAL SYSTEMS; LOGIC GATES; MATHEMATICAL MODELS; NETWORKS (CIRCUITS); OPTIMIZATION;

BINARY ADDITIONS; FACTORIZATIONS; LING PSEUDO CARRY METHOD; PARALLEL PREFIX METHOD;

DIGITAL ARITHMETIC;

EID: 21644432589     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. O.J. Bedrij, "Carry Select Adder", IRE Trans., EC-11, pp.340-346, June 1962.
2. R.C. Jackson and S. Talwar, "High Speed Adder", US Patent Application, No. 60/436,179, Dec. 2002.
3. R.C. Jackson and S. Talwar, "A Logic Circuit and Method for Carry and Sum Generation and Method of Designing Such a Logic Circuit", US Patent Application, Nov. 2003.
4. S. Knowles, "A Family of Adders", Proc. 14th IEEE Symp. on Computer Arithmetic, pp.30-34, 1999.
5. P.M. Kogge and H.S. Stone,"A Parallel Algorithm for Efficient Solution of a General Class of Recurrence Equations", IEEE Trans. Computers, Vol. C-22, No. 8, pp.786-793, Aug. 1973.
6. R.E. Ladner and M.J. Fischer, "Parallel Prefix Computatiom", Journal of ACM, Vol. 27, No.4, pp.831-838, Oct. 1980.
7. H. Ling, "High Speed Binary Adder", IBM Journal of Research and Developement, Vol. 25, No. 3, pp. 156-166, 1981.
8. J. Sklansky, "Conditional-Sum Addition Logic", ire TRANS., EC-9, pp. 226-231, June 1960.
9. A. Weinberger and J.L Smith, "A Logic for High-Speed Addition", Nat. Bur. Stand. Circ., 591, pp.3-12, 1958.