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Volumn , Issue , 2007, Pages 972-975

A new subthreshold leakage model for NMOS transistor stacks

Author keywords

BSIM; Estimation; Model; Static leakage; Subthreshold current; Transistor stacks

Indexed keywords

AVERAGE ERRORS; BSIM; MODEL; NEW MODEL; NMOS TRANSISTORS; NODAL VOLTAGES; SPICE SIMULATIONS; STATIC LEAKAGE; SUB-THRESHOLD LEAKAGE; SUBTHRESHOLD CURRENT; TRANSISTOR STACKS;

EID: 50049124817     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NEWCAS.2007.4487994     Document Type: Conference Paper
Times cited : (6)

References (5)
  • 1
    • 33646864552 scopus 로고    scopus 로고
    • Leakage current mechanisms and leakage reduction techniques in deep sub-micrometer CMOS circuits
    • Feb
    • Mahmoodi-Meimand H. Roy K., Mukhopadhyay S., "Leakage current mechanisms and leakage reduction techniques in deep sub-micrometer CMOS circuits," in Proceedings of the IEEE, Feb 2003, vol. 91, pp. 305-327
    • (2003) Proceedings of the IEEE , vol.91 , pp. 305-327
    • Mahmoodi-Meimand, H.1    Roy, K.2    Mukhopadhyay, S.3
  • 2
    • 0041589378 scopus 로고    scopus 로고
    • Analysis and minimization techniques for total leakage considering gate oxide leakage
    • D. S. Dongwoo Lee, David Blaauw. Analysis and minimization techniques for total leakage considering gate oxide leakage. DAC 2003:175-180,2003
    • (2003) DAC 2003 , pp. 175-180
    • Dongwoo Lee, D.S.1    Blaauw, D.2
  • 3
    • 0030146154 scopus 로고    scopus 로고
    • Power Distribution Anaylsis and Optimization of Deep Submicron CMOS Digital Circuits
    • May
    • R. X. Gu and M. I. Elmasry, "Power Distribution Anaylsis and Optimization of Deep Submicron CMOS Digital Circuits," IEEE J. Solid-State Circuits, vol. 31, no. 5, pp. 707-713, May 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , Issue.5 , pp. 707-713
    • Gu, R.X.1    Elmasry, M.I.2
  • 4
    • 84886736952 scopus 로고    scopus 로고
    • New generation of Predictive Technology Model for sub45nm design exploration
    • pp, ISQED
    • W. Zhao, Y. Cao, "New generation of Predictive Technology Model for sub45nm design exploration," pp. 585-590, ISQED, 2006. http://www.eas.asu. edu/~ptm/
    • (2006) , pp. 585-590
    • Zhao, W.1    Cao, Y.2
  • 5
    • 50049131346 scopus 로고    scopus 로고
    • BSIM3v3.0 MOSFET Model - User's Manual
    • BSIM3v3.0 MOSFET Model - User's Manual


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.