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Volumn 71, Issue 1, 2011, Pages 114-131

Leveraging workload diversity through OS scheduling to maximize performance on single-ISA heterogeneous multicore systems

Author keywords

Asymmetric single ISA processors; Heterogeneous multicore; OS scheduling; Workload characterization

Indexed keywords

SCHEDULING; SCHEDULING ALGORITHMS;

EID: 80054967516     PISSN: 07437315     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.jpdc.2010.08.020     Document Type: Article
Times cited : (34)

References (33)
  • 3
    • 27544432558 scopus 로고    scopus 로고
    • The impact of performance asymmetry in emerging multicore architectures
    • S. Balakrishnan, R. Rajwar, M. Upton, K. Lai, The impact of performance asymmetry in emerging multicore architectures, SIGARCH Comput. Archit. News 33 (2) (2005) 506-517.
    • (2005) SIGARCH Comput. Archit. News , vol.33 , Issue.2 , pp. 506-517
    • Balakrishnan, S.1    Rajwar, R.2    Upton, M.3    Lai, K.4
  • 5
    • 2642534571 scopus 로고    scopus 로고
    • StatCache: A probabilistic approach to efficient and accurate data locality analysis
    • E. Berg, E. Hagersten, StatCache: a probabilistic approach to efficient and accurate data locality analysis, in: ISPASS'04.
    • ISPASS'04
    • Berg, E.1    Hagersten, E.2
  • 7
    • 21244474546 scopus 로고    scopus 로고
    • Predicting inter-thread cache contention on a chip multi-processor architecture
    • D. Chandra, F. Guo, S. Kim, Y. Solihin, Predicting inter-thread cache contention on a chip multi-processor architecture, in: HPCA'05.
    • HPCA'05
    • Chandra, D.1    Guo, F.2    Kim, S.3    Solihin, Y.4
  • 9
    • 34248638757 scopus 로고    scopus 로고
    • Analyzing the energy-time trade-off in high-performance computing applications
    • V.W. Freeh, D.K. Lowenthal, F. Pan, N. Kappiah, R. Springer, B.L. Rountree, Analyzing the energy-time trade-off in high-performance computing applications, IEEE TPDS. 18 (6) (2007) 835-848.
    • (2007) IEEE TPDS , vol.18 , Issue.6 , pp. 835-848
    • Freeh, V.W.1    Lowenthal, D.K.2    Pan, F.3    Kappiah, N.4    Springer, R.5    Rountree, B.L.6
  • 10
    • 84865792581 scopus 로고    scopus 로고
    • Preparing for the second stage of multi-core hardware: Asymmetric (Heterogeneous) cores
    • M. Gillespie, Preparing for the second stage of multi-core hardware: asymmetric (Heterogeneous) cores, Intel White Paper, 2008.
    • (2008) Intel White Paper
    • Gillespie, M.1
  • 11
    • 48249118853 scopus 로고    scopus 로고
    • Amdahl's law in the multicore era
    • M.D. Hill, M.R. Marty, Amdahl's law in the multicore era, IEEE Computer 41 (7) (2008) 33-38.
    • (2008) IEEE Computer , vol.41 , Issue.7 , pp. 33-38
    • Hill, M.D.1    Marty, M.R.2
  • 12
    • 0024903997 scopus 로고
    • Evaluating associativity in CPU caches
    • M.D. Hill, A.J. Smith, Evaluating associativity in CPU caches, IEEE TC 38 (12) (1989) 1612-1630.
    • (1989) IEEE TC , vol.38 , Issue.12 , pp. 1612-1630
    • Hill, M.D.1    Smith, A.J.2
  • 13
    • 34548329985 scopus 로고    scopus 로고
    • Microarchitecture-independent workload characterization
    • K. Hoste, L. Eeckhout, Microarchitecture-independent workload characterization, IEEE Micro 27 (3) (2007) 63-72.
    • (2007) IEEE Micro , vol.27 , Issue.3 , pp. 63-72
    • Hoste, K.1    Eeckhout, L.2
  • 14
    • 0038346237 scopus 로고    scopus 로고
    • Positional adaptation of processors: Application to energy reduction
    • M.C. Huang, J. Renau, J. Torrellas, Positional adaptation of processors: application to energy reduction, in: ISCA'03.
    • ISCA'03
    • Huang, M.C.1    Renau, J.2    Torrellas, J.3
  • 16
    • 77954512029 scopus 로고    scopus 로고
    • Performance implications of cache affinity on multicore processors
    • V. Kazempour, A. Fedorova, P. Alagheband, Performance implications of cache affinity on multicore processors, in: Euro-Par'08.
    • Euro-Par'08
    • Kazempour, V.1    Fedorova, A.2    Alagheband, P.3
  • 18
    • 84944403811 scopus 로고    scopus 로고
    • Single-ISA heterogeneous multi-core architectures: The potential for processor power reduction
    • R. Kumar, K.I. Farkas, N.P. Jouppi, P. Ranganathan, D.M. Tullsen, Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction, in: MICRO 36.
    • MICRO 36
    • Kumar, R.1    Farkas, K.I.2    Jouppi, N.P.3    Ranganathan, P.4    Tullsen, D.M.5
  • 19
    • 4644370318 scopus 로고    scopus 로고
    • Single-ISA heterogeneous multi-core architectures for multithreaded workload performance
    • R. Kumar, D.M. Tullsen, P. Ranganathan, N.P. Jouppi, K.I. Farkas, Single-ISA Heterogeneous Multi-core Architectures for Multithreaded Workload Performance, in: ISCA'04.
    • ISCA'04
    • Kumar, R.1    Tullsen, D.M.2    Ranganathan, P.3    Jouppi, N.P.4    Farkas, K.I.5
  • 20
    • 77954404545 scopus 로고    scopus 로고
    • Efficient operating system scheduling for performance-asymmetric multi-core architectures
    • T. Li, D. Baumberger, D.A. Koufaty, S. Hahn, Efficient operating system scheduling for performance-asymmetric multi-core architectures, in: ICS'07.
    • ICS'07
    • Li, T.1    Baumberger, D.2    Koufaty, D.A.3    Hahn, S.4
  • 22
    • 47249139474 scopus 로고    scopus 로고
    • Using asymmetric single-ISA CMPs to save energy on operating systems
    • J.C. Mogul, J. Mudigonda, N. Binkert, P. Ranganathan, V. Talwar, Using asymmetric single-ISA CMPs to save energy on operating systems, IEEE Micro 28 (3) (2008) 26-41.
    • (2008) IEEE Micro , vol.28 , Issue.3 , pp. 26-41
    • Mogul, J.C.1    Mudigonda, J.2    Binkert, N.3    Ranganathan, P.4    Talwar, V.5
  • 24
    • 35649006026 scopus 로고    scopus 로고
    • CellSs: Making it easier to program the cell broadband engine processor
    • J.P. Perez, P. Bellens, R.M. Badia, J. Labarta, CellSs: making it easier to program the cell broadband engine processor, IBM J. Res. Dev. 51 (2007) 593-604.
    • (2007) IBM J. Res. Dev. , vol.51 , pp. 593-604
    • Perez, J.P.1    Bellens, P.2    Badia, R.M.3    Labarta, J.4
  • 25
    • 77954531074 scopus 로고    scopus 로고
    • Operating system support for mitigating software scalability bottlenecks on asymmetric multicore processors
    • J.C. Saez, A. Fedorova, M. Prieto, H. Vegas, Operating system support for mitigating software scalability bottlenecks on asymmetric multicore processors, in: Proc. of ACM Computing Frontiers'10.
    • Proc. of ACM Computing Frontiers'10
    • Saez, J.C.1    Fedorova, A.2    Prieto, M.3    Vegas, H.4
  • 29
    • 0017949328 scopus 로고
    • A comparative study of set associative memory mapping algorithms and their use for cache and main memory
    • A.J. Smith, A comparative study of set associative memory mapping algorithms and their use for cache and main memory, IEEE Trans. Softw. Eng. 4 (2) (1978) 121-130.
    • (1978) IEEE Trans. Softw. Eng. , vol.4 , Issue.2 , pp. 121-130
    • Smith, A.J.1
  • 30
    • 67650088533 scopus 로고    scopus 로고
    • RapidMRC: Approximating L2 miss rate curves on commodity systems for online optimizations
    • D.K. Tam, R. Azimi, L.B. Soares, M. Stumm, RapidMRC: approximating L2 miss rate curves on commodity systems for online optimizations, in: ASPLOS'09, pp. 121-132.
    • ASPLOS'09 , pp. 121-132
    • Tam, D.K.1    Azimi, R.2    Soares, L.B.3    Stumm, M.4
  • 31
    • 85184357698 scopus 로고    scopus 로고
    • Variation-aware application scheduling and power management for chip multiprocessors
    • R. Teodorescu, J. Torrellas, Variation-aware application scheduling and power management for chip multiprocessors, in: ISCA'08.
    • ISCA'08
    • Teodorescu, R.1    Torrellas, J.2
  • 33
    • 77952248898 scopus 로고    scopus 로고
    • Addressing cache contention in multicore processors via scheduling
    • S. Zhuravlev, S. Blagodurov, A. Fedorova, Addressing cache contention in multicore processors via scheduling, in: ASPLOS'10.
    • ASPLOS'10
    • Zhuravlev, S.1    Blagodurov, S.2    Fedorova, A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.