Operating system support for mitigating software scalability bottlenecks on asymmetric multicore processors

CF 2010 - Proceedings of the 2010 Computing Frontiers Conference

Volumn , Issue , 2010, Pages 31-40

  Saez, Juan Carlos ^a   Fedorova, Alexandra ^b   Prieto, Manuel ^a   Vegas, Hugo ^a  

^a UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

^b SIMON FRASER UNIVERSITY   (Canada)

Author keywords

asymmetric multicore; operating systems; scheduling

Indexed keywords

FREQUENCY-SCALING; INSTRUCTION SET ARCHITECTURE; MULTI CORE; MULTI-CORE PROCESSOR; OPERATING SYSTEM SUPPORT; OPERATING SYSTEMS; OUT OF ORDER; PARALLEL APPLICATION; SCHEDULING POLICIES;

COMPUTER ARCHITECTURE; SCHEDULING;

COMPUTER OPERATING SYSTEMS;

EID: 77954531074     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1787275.1787281     Document Type: Conference Paper

References (19)

1. T. Anderson. The Performance of Spin Lock Alternatives for Shared-Money Multiprocessors. IEEE TPDS, 1(1):6-16, 1990.
2. M. Annavaram, E. Grochowski, and J. Shen. Mitigating Amdahl's Law through EPI Throttling. In Proc. of ISCA'05, pages 298-309, 2005.
3. D. H. Bailey, E. Barszcz, and J. T. Barton et al. The NAS parallel benchmarks-summary and preliminary results. In Supercomputing '91, pages 158-165, 1991.
4. S. Balakrishnan, R. Rajwar, M. Upton, and K. Lai. The Impact of Performance Asymmetry in Emerging Multicore Architectures. SIGARCH CAN, 33(2):506-517, 2005.
5. M. Becchi and P. Crowley. Dynamic Thread Assignment on Heterogeneous Multiprocessor Architectures. In Proc. of Computing Frontiers '06, pages 29-40, 2006.
6. C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC Benchmark Suite: Characterization and Architectural Implications. In Proc. of PACT'08, October 2008.
7. M. D. Hill and M. R. Marty. Amdahl's Law in the Multicore Era. IEEE Computer, 41(7):33-38, 2008.
8. R. Kumar, K. I. Farkas, and N. Jouppi et al. Single-ISA Heterogeneous Multi-Core Architectures: the Potential for Processor Power Reduction. In Proc. of MICRO 36, 2003.
9. R. Kumar, D. M. Tullsen, and P. Ranganathan et al. Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance. In Proc. of ISCA '04.
10. T. Li, D. Baumberger, and D. A. Koufaty et al. Efficient Operating System Scheduling for Performance-Asymmetric Multi-Core Architectures. In Proc. of SC '07, pages 1-11.
11. T. Li, A. R. Lebeck, and D. J. Sorin. Spin Detection Hardware for Improved Management of Multithreaded Systems. IEEE TPDS, 17(6):508-521, 2006.
12. T. Morad, U. Weiser, and A. Kolody. ACCMP - Asymmetric Cluster Chip Multi-Processing. TR CCIT, 2004.
13. R. Narayanan, B. Ozisikyilmaz, and J. Z. et al. MineBench: A Benchmark Suite for Data Mining Workloads. 2006.
14. M. A. Olson, K. Bostic, and M. Seltzer. Berkeley DB. In Proc. of USENIX, pages 43-43, 1999.
15. J. C. Saez, M. Prieto, A. Fedorova, and S. Blagodourov. A Comprehensive Scheduler for Asymmetric Multicore Systems. In Proc. of ACM Eurosys '10, 2010.
16. D. Shelepov, J. C. Saez, and S. Jeffery et al. HASS: a Scheduler for Heterogeneous Multicore Systems. ACM Operating System Review, 43(2), 2009.
17. M. A. Suleman, O. Mutlu, M. K. Qureshi, and Y. N. Patt. Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures. In Proc. of ASPLOS '09, pages 253-264, 2009.
18. R. Teodorescu and J. Torrellas. Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors. In Proc. of ISCA '08, 2008.
19. R. van der Pas. The OMPlab on Sun Systems. In Proc. of IWOMP'05, 2005.