A power-optimized 64-bit priority encoder utilizing parallel priority look-ahead

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2004, Pages

  Kun, Cheong ^a   Quan, Shaolei ^a   Mason, Andrew ^a  

^a MICHIGAN STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; COMPUTER SYSTEMS; FUNCTIONS; INTEGRATED CIRCUITS; OPTIMIZATION; TRANSISTORS;

DYNAMIC CIRCUITS; POWER CONSUMPTION; PRIOITY ENCODERS (PE);

ENCODING (SYMBOLS);

EID: 4344651302     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 3rd Edition, Morgan Kaufmann, New York, 2001.
2. C.H. Huang, and J.S. Wang, "High-Performance and Power-Efficient CMOS Comparators," IEEE J. Solid-State Circuits, vol.38, pp 254 -262, Feb. 2003.
3. C.H. Huang, J.S. Wang, and Y.C. Huang, "Design of High Performance CMOS Priority Encoders and Incrementer/Decrementers Using Multilevel Lookahead and Multilevel Folding Techniques," IEEE J. Solid-State Circuits, vol.37, pp. 63-76, Jan. 2002.
4. J. G. Delgado-Frias and J. Nyathi, "A high-performance encoder with priority lookahead," IEEE Trans. Circuit Sys. I, vol.47, pp. 1390-1393, Sept. 2000.
5. J.S. Wang and C.H. Huang, "High-speed and low-power CMOS priority encoders," IEEE J. Solid-State Circuits, vol.35, pp1511-1514, Oct. 2000.
6. K. Martin, Digital Integrated Circuit Design, Oxford, New York, 2000.