Adaptive line placement with the set balancing cache

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2009, Pages 529-540

  Rolán, Dyer ^a   Fraguela, Basilio B ^a   Doallo, Ramón ^a  

^a UNIVERSITY OF A CORUÑA   (Spain)

Author keywords

Adaptivity; Balancing; Cache; Performance

Indexed keywords

ADAPTIVITY; CACHE PERFORMANCE; LINE PLACEMENT; MEMORY ACCESS; MEMORY HIERARCHY; MISS-RATE; NON-UNIFORM DISTRIBUTION; WORKING SET;

CACHE MEMORY;

EID: 76749164849     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1669112.1669178     Document Type: Conference Paper

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