Low power motion estimation with probabilistic computing

Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011

Volumn , Issue , 2011, Pages 176-181

  Dhoot, Charvi ^a,b   Mooney, Vincent J ^b,c,d   Chau, Lap Pui ^b   Chowdhury, Shubhajit Roy ^a  

^a INTERNATIONAL INSTITUTE OF INFORMATION TECHNOLOGY   (India)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^c NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^d GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Error resilient design; Low power design; Motion estimation; PCMOS architecture; Probabilistic computing

Indexed keywords

ENERGY EFFICIENT COMPUTING; ERROR-RESILIENT; FULL SEARCH BLOCK MATCHING; FUTURE TECHNOLOGIES; LOW POWER; LOW-POWER DESIGN; MOORE'S LAW; MOTION VECTORS; NANO METER RANGE; NOISE SOURCE; PCMOS ARCHITECTURE; PROBABILISTIC COMPUTING; SIGNAL PROCESSING APPLICATIONS;

ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY CONSERVATION; ESTIMATION; MOTION COMPENSATION; SIGNAL PROCESSING;

MOTION ESTIMATION;

EID: 80052566978     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2011.58     Document Type: Conference Paper

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