Modeling multi-output filtering effects in PCMOS

Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

Volumn , Issue , 2011, Pages 414-417

  Singh, Anshul ^a,b   Basu, Arindam ^b   Ling, Keck Voon ^b   Mooney, Vincent J ^b,c,d  

^a INTERNATIONAL INSTITUTE OF INFORMATION TECHNOLOGY   (India)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^c NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^d GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILDING BLOCKES; CARRY SELECT ADDERS; CASCADE STRUCTURES; ERROR RATE; FILTERING EFFECTS; FULL ADDERS; MULTI-OUTPUT; NEW MODEL; PREDICT ERRORS; REASONABLE ACCURACY; WALLACE TREE;

ADDERS; FORECASTING; MULTIPLYING CIRCUITS;

STRUCTURAL DESIGN;

EID: 79959508655     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VDAT.2011.5783561     Document Type: Conference Paper

References (7)

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