Low power probabilistic floating point multiplier design

Proceedings - 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011

Volumn , Issue , 2011, Pages 182-187

  Gupta, Aman ^a,b   Mandavalli, Satyam ^a   Mooney, Vincent J ^b,c,d   Ling, Keck Voon ^b   Basu, Arindam ^b   Johan, Henry ^a,b   Tandianus, Budianto ^a,b  

^a INTERNATIONAL INSTITUTE OF INFORMATION TECHNOLOGY   (India)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^c NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^d GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Floating point multiplication; Probabilistic computation

Indexed keywords

COMPUTER GRAPHICS APPLICATIONS; DIGITAL LOGIC; ENERGY-EFFICIENT DESIGN; FLOATING POINT MULTIPLICATION; FLOATING POINTS; LOW POWER; PERCEPTUAL QUALITY; PROBABILISTIC COMPUTATION; RAY-TRACING ALGORITHM;

ALGORITHMS; COMPUTER GRAPHICS; DIGITAL ARITHMETIC; FREQUENCY MULTIPLYING CIRCUITS;

PROBABILISTIC LOGICS;

EID: 80052562791     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2011.54     Document Type: Conference Paper

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