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Volumn 32, Issue 2, 2011, Pages 125-127

Sensitivity of threshold voltage to nanowire width variation in junctionless transistors

Author keywords

All around gate (AAG); body thickness; Bosch process; bulk substrate; fluctuation; gated resistor; junctionless transistor; silicon nanowire (SiNW); threshold voltage; variation; width

Indexed keywords

ALL-AROUND GATE; BODY THICKNESS; BOSCH PROCESS; BULK SUBSTRATES; FLUCTUATION; GATED RESISTOR; JUNCTIONLESS TRANSISTOR; SILICON NANOWIRE (SINW); VARIATION; WIDTH;

EID: 79151480956     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2010.2093506     Document Type: Article
Times cited : (316)

References (12)
  • 7
    • 0242332710 scopus 로고    scopus 로고
    • Sensitivity of double-gate and FinFET devices to process variations
    • Nov.
    • S. Xiong and J. Bokor, "Sensitivity of double-gate and FinFET devices to process variations," IEEE Trans. Electron Devices, vol. 50, no. 11, pp. 2255-2261, Nov. 2003.
    • (2003) IEEE Trans. Electron Devices , vol.50 , Issue.11 , pp. 2255-2261
    • Xiong, S.1    Bokor, J.2
  • 10
    • 67349225959 scopus 로고    scopus 로고
    • Vertically stacked silicon nanowire transistors fabricated by inductive plasma etching and stress-limited oxidation
    • May
    • R. M. Y. Ng, T. Wang, F. Liu, X. Zuo, J. He, and M. Chan, "Vertically stacked silicon nanowire transistors fabricated by inductive plasma etching and stress-limited oxidation," IEEE Electron Device Lett., vol. 30, no. 5, pp. 520-522, May 2009.
    • (2009) IEEE Electron Device Lett. , vol.30 , Issue.5 , pp. 520-522
    • Ng, R.M.Y.1    Wang, T.2    Liu, F.3    Zuo, X.4    He, J.5    Chan, M.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.