-
1
-
-
0033750493
-
Ultra-thin-body SOI MOSFET for deep-sub-tenth micron era
-
May
-
Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bokor, and C. Hu, "Ultra-thin-body SOI MOSFET for deep-sub-tenth micron era," IEEE Electron Device Lett., vol. 21, no. 5, pp. 254-255, May 2000.
-
(2000)
IEEE Electron Device Lett.
, vol.21
, Issue.5
, pp. 254-255
-
-
Choi, Y.-K.1
Asano, K.2
Lindert, N.3
Subramanian, V.4
King, T.-J.5
Bokor, J.6
Hu, C.7
-
2
-
-
29044440093
-
FinFET-A self-aligned double-gate MOSFET scalable to 20 nm
-
Dec.
-
D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Bokor, and C. Hu, "FinFET-A self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, Dec. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, Issue.12
, pp. 2320-2325
-
-
Hisamoto, D.1
Lee, W.-C.2
Kedzierski, J.3
Takeuchi, H.4
Asano, K.5
Kuo, C.6
Anderson, E.7
King, T.-J.8
Bokor, J.9
Hu, C.10
-
3
-
-
33646271349
-
High-performance fully depleted silicon nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices
-
May
-
N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar, G. Q. Lo, N. Balasubramanian, and D.-L. Kwong, "High-performance fully depleted silicon nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices," IEEE Electron Device Lett., vol. 27, no. 5, pp. 383-385, May 2006.
-
(2006)
IEEE Electron Device Lett.
, vol.27
, Issue.5
, pp. 383-385
-
-
Singh, N.1
Agarwal, A.2
Bera, L.K.3
Liow, T.Y.4
Yang, R.5
Rustagi, S.C.6
Tung, C.H.7
Kumar, R.8
Lo, G.Q.9
Balasubramanian, N.10
Kwong, D.-L.11
-
4
-
-
59849089910
-
Junctionless multigate field-effect transistor
-
Feb.
-
C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J. P. Colinge, "Junctionless multigate field-effect transistor," Appl. Phys. Lett., vol. 94, no. 5, p. 053 511, Feb. 2009.
-
(2009)
Appl. Phys. Lett.
, vol.94
, Issue.5
, pp. 053511
-
-
Lee, C.-W.1
Afzalian, A.2
Akhavan, N.D.3
Yan, R.4
Ferain, I.5
Colinge, J.P.6
-
5
-
-
77949275137
-
Nanowire transistors without junctions
-
Mar.
-
J.-P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O'Neill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy, and R. Murphy, "Nanowire transistors without junctions," Nat. Nanotech-nol., vol. 5, no. 3, pp. 225-229, Mar. 2010.
-
(2010)
Nat. Nanotech-nol.
, vol.5
, Issue.3
, pp. 225-229
-
-
Colinge, J.-P.1
Lee, C.-W.2
Afzalian, A.3
Akhavan, N.D.4
Yan, R.5
Ferain, I.6
Razavi, P.7
O'Neill, B.8
Blake, A.9
White, M.10
Kelleher, A.-M.11
McCarthy, B.12
Murphy, R.13
-
7
-
-
0242332710
-
Sensitivity of double-gate and FinFET devices to process variations
-
Nov.
-
S. Xiong and J. Bokor, "Sensitivity of double-gate and FinFET devices to process variations," IEEE Trans. Electron Devices, vol. 50, no. 11, pp. 2255-2261, Nov. 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, Issue.11
, pp. 2255-2261
-
-
Xiong, S.1
Bokor, J.2
-
8
-
-
36549030295
-
Experimental evaluation of effects of channel doping on characteristics of FinFETs
-
Dec.
-
K. Endo, Y. Ishikawa, Y. Liu, M. Masahara, T. Matsukawa, S.-I. O'uchi, K. Ishii, H. Yamauchi, J. Tsukada, and E. Suzuki, "Experimental evaluation of effects of channel doping on characteristics of FinFETs," IEEE Electron Device Lett., vol. 28, no. 12, pp. 1123-1125, Dec. 2007.
-
(2007)
IEEE Electron Device Lett.
, vol.28
, Issue.12
, pp. 1123-1125
-
-
Endo, K.1
Ishikawa, Y.2
Liu, Y.3
Masahara, M.4
Matsukawa, S.-I.5
O'Uchi, K.6
Ishii, H.7
Yamauchi, J.8
Tsukada, E.9
Suzuki, T.10
-
9
-
-
77249173867
-
Reduced electric field in junction-less transistors
-
Feb.
-
J.-P. Colinge, C.-W. Lee, I. Ferain, N. D. Akhavan, R. Yan, P. Razavi, R. Yu, A. N. Nazarov, and R. T. Doria, "Reduced electric field in junction-less transistors," Appl. Phys. Lett., vol. 96, no. 7, p. 073 510, Feb. 2010.
-
(2010)
Appl. Phys. Lett.
, vol.96
, Issue.7
, pp. 073510
-
-
Colinge, J.-P.1
Lee, C.-W.2
Ferain, I.3
Akhavan, N.D.4
Yan, R.5
Razavi, P.6
Yu, R.7
Nazarov, A.N.8
Doria, R.T.9
-
10
-
-
67349225959
-
Vertically stacked silicon nanowire transistors fabricated by inductive plasma etching and stress-limited oxidation
-
May
-
R. M. Y. Ng, T. Wang, F. Liu, X. Zuo, J. He, and M. Chan, "Vertically stacked silicon nanowire transistors fabricated by inductive plasma etching and stress-limited oxidation," IEEE Electron Device Lett., vol. 30, no. 5, pp. 520-522, May 2009.
-
(2009)
IEEE Electron Device Lett.
, vol.30
, Issue.5
, pp. 520-522
-
-
Ng, R.M.Y.1
Wang, T.2
Liu, F.3
Zuo, X.4
He, J.5
Chan, M.6
-
11
-
-
77957859786
-
A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device
-
H.-T. Lue, T.-H. Hsu, Y.-H. Hsiao, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, S.-Y. Wang, J.-Y. Hsieh, L.-W. Yang, T. Yang, K.-C. Chen, K.-Y. Hsieh, and C.-Y. Lu, "A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device," in VLSI Symp. Tech. Dig., 2010, pp. 131-132.
-
(2010)
VLSI Symp. Tech. Dig.
, pp. 131-132
-
-
Lue, H.-T.1
Hsu, T.-H.2
Hsiao, Y.-H.3
Hong, S.P.4
Wu, M.T.5
Hsu, F.H.6
Lien, N.Z.7
Wang, S.-Y.8
Hsieh, J.-Y.9
Yang, L.-W.10
Yang, T.11
Chen, K.-C.12
Hsieh, K.-Y.13
Lu, C.-Y.14
-
12
-
-
78149266578
-
Junctionless nanowire transistor (JNT): Properties and design guideline
-
A. Kranti, R. Yan, C.-W. Lee, I. Ferain, R. Yu, N. D. Akhavan, P. Razavi, and J. P. Colinge, "Junctionless nanowire transistor (JNT): Properties and design guideline," in Proc. ESSDERC Conf., 2010, pp. 357-360.
-
(2010)
Proc. ESSDERC Conf.
, pp. 357-360
-
-
Kranti, A.1
Yan, R.2
Lee, C.-W.3
Ferain, I.4
Yu, R.5
Akhavan, N.D.6
Razavi, P.7
Colinge, J.P.8
|