Evaluating on-chip interconnects for low operating frequency silicon neuron arrays

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2011, Pages 2437-2440

  Cassidy, Andrew ^a   Murray, Thomas ^a   Andreou, Andreas G ^a   Georgiou, Julius ^b  

^a Johns Hopkins University   (United States)

^b UNIVERSITY OF CYPRUS   (Cyprus)

Author keywords

[No Author keywords available]

Indexed keywords

ADDRESS-EVENT REPRESENTATION; BANDWIDTH LIMITATION; CLOCK FREQUENCY; HIGH DENSITY; LOW POWER; MESH NETWORK; ON CHIPS; ON-CHIP INTERCONNECTS; OPERATING FREQUENCY; SILICON NEURON; SINGLE CHIPS; SUBTHRESHOLD; TIME MULTIPLEXED;

NEURAL NETWORKS; SWITCHING CIRCUITS;

ELECTRIC NETWORK ANALYSIS;

EID: 79960878446     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2011.5938096     Document Type: Conference Paper

References (14)

1. K. A. Boahen, "Point-to-point connectivity between neuromorphic chips using address events," IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 47, no. 5, pp. 416-434, 2000.
2. D. Goldberg, G. Cauwenberghs, and A. Andreou, "Probabilistic synaptic weighting in a reconfigurable network of VLSI integrate-and-fire neurons,"Neural Networks, vol. 14, pp. 781-793, 2001.
3. R. J. Vogelstein, U. Mallik, E. Culurciello, G. Cauwenberghs, and R. Etienne-Cummings, "A Multichip Neuromorphic System for Spike-Based Visual Information Processing," Neural Comp., vol. 19, no. 9, pp. 2281-2300, 2007.
4. G. Indiveri, E. Chicca, and R. Douglas, "A VLSI reconfigurable network of integrate-and-fire neurons with spike-based learning synapses,"Proceedings of 12th European Symposium on Artificial Neural Networks (ESANN04), pp. 405-410, 2004.
5. T. Choi, P. Merolla, J. Arthur, K. Boahen, and B. Shi, "Neuromorphic implementation of orientation hypercolumns," IEEE Transactions on Circuits and Systems I, vol. 52, no. 6, pp. 1049-1060, 2005.
6. A. Cassidy, S. Denham, P. Kanold, and A. Andreou, "FPGA Based Silicon Spiking Neural Array," IEEE Biomedical Circuits and Systems Conference, (BioCAS), pp. 75-78, Nov. 2007.
7. A. Cassidy and A. G. Andreou, "Dynamical Digital Silicon Neurons,"in IEEE International Conference on Biomedical Circuits and Systems (BioCAS), Baltimore, Nov 2008.
8. J. Schemmel, J. Fieres, and K. Meier, "Wafer-scale integration of analog neural networks," in IEEE International Joint Conference on Neural Networks, (IJCNN), 2008, pp. 431-438.
9. E. Culurciello and A. Andreou, "A comparative study of access topologies for chip-level address-event communication channels," IEEE Transactions on Neural Networks, vol. 14, no. 5, pp. 1266-1277, 2003.
10. A. Wang and A. Chandrakasan, "A 180-mV subthreshold FFT processor using a minimum energy design methodology," IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp. 310-319, 2005.
11. S. Hanson, B. Zhai, M. Seok, B. Cline, K. Zhou, M. Singhal, M. Minuth, J. Olson, L. Nazhandali, T. Austin, et al., "Exploring variability and performance in a sub-200-mV processor," IEEE Journal of Solid State Circuits, vol. 43, no. 4, p. 881, 2008.
12. D. Gross and C. M. Harris, Fundamentals of queueing theory, 3rd ed. John Wiley & Sons, Inc., 1998.
13. J. Medhi, Stochastic models in queueing theory. Academic Press Boston, Massachusetts, USA, 1991.
14. A. DeHon and R. Rubin, "Design of FPGA interconnect for multilevel metallization," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 10, pp. 1038-1050, 2004.