Design of FPGA interconnect for multilevel metallization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 12, Issue 10, 2004, Pages 1038-1050

  Dehon, André ^a   Rubin, Raphael ^a  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Field programmable gate array (FPGA); Hierarchical; Interconnect; Mesh of trees (MoT); Multilevel metallization; Rent's rule

Indexed keywords

METALLIZING; SILICON; SWITCHING; TOPOLOGY; VLSI CIRCUITS;

INTERCONNECT LAYERS; MESH-OF-TREES (MOT); MULTILEVEL METALLIZATION;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 6344263535     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.827562     Document Type: Conference Paper

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