Thermal-aware system-level modeling and management for Multi-Processor Systems-on-Chip

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2011, Pages 2481-2484

  Zanini, Francesco ^a   Atienza, David ^a   Benini, Luca ^b   De Micheli, Giovanni ^a  

^a EPFL   (Switzerland)

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN COMPLEXITY; DISCRETE-TIME OPTIMAL CONTROL PROBLEM; ELECTRONICS MARKETS; GROWING DEMAND; HIGH PERFORMANCE SYSTEMS; MULTI-PROCESSORS; MULTICORE ARCHITECTURES; OPERATING TEMPERATURE; SYSTEM LEVEL DESIGN; SYSTEM LEVELS; SYSTEM-LEVEL MODELING; SYSTEMS ON CHIPS; THERMAL MODELING; TIME VARYING;

DESIGN; MICROPROCESSOR CHIPS; MODEL PREDICTIVE CONTROL; MULTIPROCESSING SYSTEMS; PREDICTIVE CONTROL SYSTEMS; THERMOANALYSIS;

DISCRETE TIME CONTROL SYSTEMS;

EID: 79960854180     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2011.5938107     Document Type: Conference Paper

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