CMOS technology scaling considerations for multi-gbps optical receivers with integrated photodetectors

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 8, 2011, Pages 1832-1842

  Carusone, Anthony Chan ^a   Yasotharan, Hemesh ^a   Kao, Tony ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

CMOS photodetectors; decision feedback equalization; nanoscale CMOS; optical communication

Indexed keywords

ADVANCED PROCESS; CMOS PHOTODETECTORS; CMOS TECHNOLOGY; DECISION FEEDBACK EQUALIZATION; DECISION-FEEDBACK EQUALIZATIONS; EQUALIZATION TECHNIQUES; INTEGRATED PHOTODETECTOR; LOW COSTS; MULTI-GBPS; NANOSCALE CMOS; PHOTODETECTOR BANDWIDTH; PHOTODETECTOR STRUCTURE; RESPONSIVITY; SCALED CMOS; TECHNOLOGY SCALING;

INTEGRATION; NANOSTRUCTURED MATERIALS; NANOTECHNOLOGY; OPTICAL COMMUNICATION; OPTOELECTRONIC DEVICES; PHOTODETECTORS; TECHNOLOGY;

CMOS INTEGRATED CIRCUITS;

EID: 79960834035     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2157254     Document Type: Conference Paper

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