DART: A programmable architecture for NoC simulation on FPGAs

NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip

Volumn , Issue , 2011, Pages 145-152

  Wang, Danyao ^a   Jerger, Natalie Enright ^a   Steffan, J Gregory ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

FPGA; Network on Chip; simulation

Indexed keywords

BUFFER SIZES; CONTROL MECHANISM; FPGA DESIGN; FPGA IMPLEMENTATIONS; FUNDAMENTAL COMPONENT; MULTI CORE; NETWORK-ON-CHIP; NOC DESIGN; ON CHIP COMMUNICATION; ON CHIPS; PERFORMANCE TRADE-OFF; PROGRAMMABLE ARCHITECTURES; SIMULATION; SIMULATION ACCURACY; SIMULATION ARCHITECTURE; SIMULATION ENGINE; SOFTWARE SIMULATOR;

COMPUTER SIMULATION; COMPUTER SOFTWARE; DESIGN; FLOW CONTROL; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; TELECOMMUNICATION SYSTEMS; VLSI CIRCUITS;

ROUTERS;

EID: 79960296419     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1999946.1999970     Document Type: Conference Paper

References (21)

1. N. Agarwal et al., "GARNET: A detailed on-chip network model inside a full-system simulator," in ISPASS, April 2009.
2. E. Chung et al., "PROToFLEX: FPGA-accelerated Hybrid Functional Simulator," in IPDPS, March 2007.
3. W. Dally and B. Towles, "Route packets, not wires: on-chip interconnection networks," in Proc. Design Automation Conference, 2001.
4. -, Principles and Practices of Interconnection Networks. Morgan Kaufmann Publishers Inc., 2003.
5. W. Dally, "Express cubes: Improving the performance of k-ary n-cube interconnection networks," IEEE TOCs, pp. 1016-1023, 1991.
6. N. Genko et al., "A complete network-on-chip emulation framework," in DATE, March 2005.
7. N. Hardavellas et al., "SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture," SIGMETRICS Perform. Eval. Rev., vol. 31, no. 4, pp. 31-34, 2004.
8. Y. Krasteva et al., "A Fast Emulation-Based NoC Prototyping Framework," in RECONFIG, Dec. 2008.
9. M. Lis et al., "Scalable, accurate NoC simulation for the 1000-core era," in ISPASS, April 2011.
10. M. M. K. Martin et al., "Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset," SIGARCH Comput. Archit. News, vol. 33, no. 4, pp. 92-99, 2005.
11. V. Pai, S. Lotlikar, and P. Gratz, "AcENoCs: A configurable HW/SW platform for FPGA accelerated NoC emulation," in IEEE International Conference on VLSI Design, Jan 2011.
12. L. Peh and W. Dally, "A delay model and speculative architecture for pipelined routers," in HPCA, 2001.
13. M. Pellauer et al., "A-Ports: An Efficient Abstraction for Cycle-Accurate Performance Models on FPGAs," in FPGA, Feb. 2008.
14. M. Pellauer et al., "HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing," in HPCA, February 2011.
15. V. Puente et al., "SICOSYS: an integrated framework for studying interconnection network performance in multiprocessor systems," in Euromicro Workshop on Paral. and Distr. Processing, 2002.
16. G. Schelle and D. Grunwald, "Onchip Interconnect Exploration for Multicore Processors Utilizing FPGAs," in WARFP, 2006.
17. Z. Tan et al., "RAMP Gold: An FPGA-based architecture simulator for multiprocessors," in Proc. Design Automation Conference, 2010, pp. 463-468.
18. Z. Tan et al., "A Case for FAME: FPGA Architecture Model Execution," in ISCA, May 2010.
19. D. Wang, N. Enright Jerger, and J. Steffan, "DART: Fast and Flexible NoC Simulation using FPGAs," in WARP, 2010.
20. P. Wolkotte, P. Holzenspies, and G. Smit, "Fast, Accurate and Detailed NoC Simulations," in First Int'l Symp. on Networks-on-Chip, May 2007.
21. Xilinx, Inc., "Xilinx University Program Virtex-II Pro Development System Hardware Reference Manual," 2008, http://www.xilinx.com/univ/XUPV2P/ Documentation/ug069.pdf.