A fast emulation-based NoC prototyping framework

Proceedings - 2008 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2008

Volumn , Issue , 2008, Pages 211-216

  Krasteva, Yana E ^a   Criado, Francisco ^a   La Torre, Eduardo De ^a   Riesgo, Teresa ^a  

^a UNIVERSIDAD POLITÉCNICA DE MADRID   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

BUILDING ELEMENTS; DATA MEASURING; DESIGN EXPLORATIONS; DESIGN SPACE EXPLORATIONS; EMULATION PLATFORMS; FPGA EMULATIONS; NETWORK ON CHIPS; PARTIAL RECONFIGURATIONS; PROTOTYPING; RE-CONFIGURABLE; STATE-OF-THE ARTS;

ELECTRIC NETWORK TOPOLOGY; SPACE RESEARCH;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 62349103965     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ReConFig.2008.74     Document Type: Conference Paper

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