Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories

Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP

Volumn , Issue , 2008, Pages 111-122

  Baskaran, Muthu Manikandan ^a   Ramanujam, J ^b   Bondhugula, Uday ^a   Rountev, Atanas ^a   Krishnamoorthy, Sriram ^a   Sadayappan, P ^a  

^a Ohio State University   (United States)

^b Louisiana State University   (United States)

Author keywords

Data movement; Graphics processor unit; Multi level tiling; Scratchpad memory

Indexed keywords

ARRAY ACCESS FUNCTIONS; AUTOMATIC DETERMINATION; CELL PROCESSOR; COMPUTATIONAL POWER; DATA MOVEMENTS; FAST MEMORY; GRAPHICS PROCESSOR UNITS; LOCAL MEMORIES; MULTI-LEVEL; MULTI-LEVEL TILING; MULTIPLE LEVELS; OFF-CHIP MEMORIES; ON CHIP MEMORY; ON CHIPS; SCRATCH PAD MEMORY; TILE SIZE;

AUTOMATIC PROGRAMMING; COMPUTER PROGRAMMING LANGUAGES; IMAGE CODING; INFORMATION MANAGEMENT; MEMORY ARCHITECTURE; PARALLEL ARCHITECTURES; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS;

PARALLEL PROGRAMMING;

EID: 79959456077     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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