Multi-level tiling: M for the price of one

Proceedings of the 2007 ACM/IEEE Conference on Supercomputing, SC'07

Volumn , Issue , 2007, Pages

  Kim, DaeGon ^a   Renganarayanan, Lakshminarayanan ^a   Rostron, Dave ^a   Rajopadhye, Sanjay ^a   Strout, Michelle Mills ^a  

^a Colorado State University   (United States)

Author keywords

Data locality; Multi level tiling; Parallelism; Parameterized code generation

Indexed keywords

AUTOMATIC PROGRAMMING; BUILDING MATERIALS; CODES (SYMBOLS); COMPUTERS; NETWORK COMPONENTS;

ARBITRARY LEVELS; CODE GENERATORS; COMPILE TIMES; DATA LOCALITY; LOOP TRANSFORMATIONS; MULTI-LEVEL TILING; MULTIPLE LEVELS; OPEN SOURCES; PARALLELISM; PARAMETERIZED CODE GENERATION; PERFORMANCE IMPLEMENTATIONS; TILE SIZES; TIME OPTIMIZATIONS;

PROGRAM COMPILERS;

EID: 56749175334     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1362622.1362691     Document Type: Conference Paper

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