A dynamic timing control technique utilizing time borrowing and clock stretching

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2010, Pages

  Chae, Kwanyeob ^a   Mukhopadhyay, Saibal ^a   Lee, Chang Ho ^a   Laskar, Joy ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVATION PROBABILITIES; CLOCK FREQUENCY; CLOCK PERIOD; CLOCK STRETCHING; CMOS TECHNOLOGY; CONVENTIONAL DESIGN; CRITICAL PATHS; DETECTION SIGNAL; DYNAMIC TIMING; ERROR MANAGEMENT; ERROR TOLERANT; HIGHER FREQUENCIES; MEASUREMENT RESULTS; OPERATING FREQUENCY; PERFORMANCE PENALTIES; POWER REDUCTIONS; SYSTEM DELAY; TIME BORROWING; TIMING ERRORS;

CMOS INTEGRATED CIRCUITS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS;

CLOCKS;

EID: 78649892580     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2010.5617392     Document Type: Conference Paper

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