SAT-based semiformal verification of hardware

Formal Methods in Computer Aided Design, FMCAD 2010

Volumn , Issue , 2010, Pages 25-32

  Agbaria, Sabih ^a   Carmi, Dan ^a   Cohen, Orly ^a   Korchemny, Dmitry ^a   Lifshits, Michael ^a   Nadel, Alexander ^a  

^a INTEL CORPORATION   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

EXPERIMENTAL DATA; FORMAL VERIFICATIONS; HARDWARE VERIFICATION; HETEROGENEOUS MODELS; LIVENESS PROPERTIES; PROPOSITIONAL FORMULAS; VERIFICATION TECHNIQUES;

ALGORITHMS; COMPUTER AIDED DESIGN; COMPUTER HARDWARE;

FORMAL METHODS;

EID: 79958747917     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (33)

1. A. Biere, A. Cimatti, E. Clarke, O. Strichman, and Y. Zhu, "Bounded model checking," Advances in Computers, vol. 58, 2003.
2. J. Bhadra, M. S. Abadir, L.-C. Wang, and S. Ray, "A survey of hybrid techniques for functional verification," in IEEE Design and Test of Computers, vol. 24, 2007, pp. 112-123.
3. K. L. McMillan, Symbolic Model Checking. Norwell, MA, USA: Kluwer Academic Publishers, 1993.
4. K. Ravi and F. Somenzi, "High density reachability analysis," in ICCAD, 1995.
5. J. Yuan, J. Shen, J. A. Abraham, and A. Aziz, "On combining formal and informal verification," in CAV, 1997, pp. 376-387. (Pubitemid 127088993)
6. R. Fraer, G. Kamhi, B. Ziv, M. Y. Vardi, and L. Fix, "Prioritized traversal: Efficient reachability analysis for verification and falsification." in CAV, 2000, pp. 389-402.
7. G. Cabodi, S. Nocco, and S. Quer, "Improving sat-based bounded model checking by means of bdd-based approximate traversals," in DATE, 2003, pp. 10 898-10 905.
8. M. K. Ganai and A. Aziz, "Rarity based guided state space search," in GLSVLSI, 2001, pp. 97-102. (Pubitemid 32456874)
9. M. Ganai, P. Yalagandula, A. Aziz, A. Kuehlmann, and V. Singhal, "Siva: A system for coverage-directed state space search," J. Electron. Test., vol. 17, no. 1, pp. 11-27, 2001. (Pubitemid 32638807)
10. C. R. Ho, M. Theobald, B. Batson, J. Grossman, S. C. Wang, J. Gagliardo, M. M. Deneroff, R. O. Dror, and D. E. Shaw, "Post-silicon debug using formal verification waypoints," in DVCon, 2009.
11. A. Kuehlmann, K. L. McMillan, and R. K. Brayton, "Probabilistic state space search," in ICCAD, 1999, pp. 574-579. (Pubitemid 30560680)
12. P. Yalagandula, V. Singhal, and A. Aziz, "Automatic lighthouse generation for directed state space search," in DATE, 2000, pp. 237-242.
13. P. Bjesse and J. H. Kukula, "Using counterexample guided abstraction refinement to find complex bugs," in DATE, 2004, pp. 156-161.
14. P. H. Ho, T. Shiple, K. Harer, J. Kukula, R. Damiano, V. Bertacco, J. Taylor, and J. Long, "Smart simulation using collaborative formal and simulation engines," in ICCAD, 2000, pp. 120-126. (Pubitemid 32188470)
15. A. Aziz, J. Kukula, and T. Shiple, "Hybrid verification using saturated simulation," in DAC, 1998, pp. 615-618.
16. D. L. Dill and C. H. Yang, "Validation with guided search of the state space," in DAC, 1998, pp. 599-604.
17. E. Cerny, A. Dsouza, K. Harer, P.-H. Ho, and T. Ma, "Supporting sequential assumptions in hybrid verification," in ASP-DAC, 2005, pp. 1035-1038.
18. M. Y. Vardi, "An automata-theoretic approach to linear temporal logic," in Proceedings of the VIII Banff Higher order workshop conference on Logics for concurrency: structure versus automata, 1996, pp. 238-266. (Pubitemid 126047609)
19. A. Biere, A. Cimatti, E. M. Clarke, M. Fujita, and Y. Zhu, "Symbolic model checking using SAT procedures instead of BDDs," in DAC, 1999, pp. 317-320.
20. E. M. Clarke, D. Kroening, J. Ouaknine, and O. Strichman, "Computational challenges in bounded model checking," Journal of Software Tools and Technology Transfer, vol. 7, no. 2, pp. 174-183, 2005. (Pubitemid 41349075)
21. R. Armoni, S. Egorov, R. Fraer, D. Korchemny, and M. Vardi, "Efficient LTL compilation for SAT-based model checking," in ICCAD, 2005.
22. J. Yuan, K. Albin, A. Aziz, and C. Pixley, "Simplifying boolean constraint solving for random simulation-vector generation," in ICCAD '02, 2002, pp. 123-127.
23. W. Wei, J. Erenrich, and B. Selman, "Towards efficient sampling: Exploiting random walk strategies," in AAAI, 2004, pp. 670-676.
24. N. Kitchen and A. Kuehlmann, "Stimulus generation for constrained random simulation," in ICCAD, 2007, pp. 258-265.
25. C. P. Gomes, A. Sabharwal, and B. Selman, "Near-uniform sampling of combinatorial spaces using XOR constraints," in NIPS, B. Schölkopf, J. C. Platt, and T. Hoffman, Eds., 2006, pp. 481-488.
26. S. Plaza, I. L. Markov, and V. Bertacco, "Random stimulus generation using entropy and XOR constraints," in DATE, 2008, pp. 664-669.
27. K. L. McMillan, "Applying SAT methods in unbounded symbolic model checking," in CAV, 2002, pp. 250-264.
28. S. K. Lahiri, R. E. Bryant, and B. Cook, "A symbolic approach to predicate abstraction," in CAV, 2003, pp. 141-153.
29. K. Pipatsrisawat and A. Darwiche, "A lightweight component caching scheme for satisfiability solvers," in SAT, 2007, pp. 294-299.
30. A. Biere, C. Artho, and V. Schuppan, "Liveness checking as safety checking." Electr. Notes Theor. Comput. Sci., vol. 66, no. 2, 2002. [Online]. Available: http://dblp.uni-trier.de/db/journals/entcs/entcs66. html#BiereAS02
31. E. M. Clarke, O. Grumberg, and D. A. Peled, Model Checking, 6th ed. MIT Press, 2008.
32. M. K. Ganai, A. Gupta, and P. Ashar, "Beyond safety: customized sat-based model checking," in DAC '05: Proceedings of the 42nd annual Design Automation Conference. New York, NY, USA: ACM, 2005, pp. 738-743. (Pubitemid 41675534)
33. M. K. Ganai, A. Aziz, and A. Kuehlmann, "Enhancing simulation with BDDs and ATPG," in DAC, 1999, pp. 385-390.