Invasive computing: An overview

Multiprocessor System-on-Chip: Hardware Design and Tool Integration

Volumn , Issue , 2011, Pages 241-268

  Teich, Jürgen ^a   Henkel, Jörg ^b   Herkersdorf, Andreas ^b   Schmitt Landsiedel, Doris ^b   Schröder Preikschat, Wolfgang ^b   Snelting, Gregor ^b  

^a UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

^b NONE

Author keywords

B (Hardware); B.7 (Hardware: Integrated Circuits); C (Computer Systems Organisation); C.1 (Computer Systems Organisation; Processor Architectures); C.3 (Computer Systems Organisation: Special Purpose and Application Based Systems)

Indexed keywords

EID: 79958138859     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/978-1-4419-6460-1_11     Document Type: Chapter

References (19)

1. Rabaey, J.M., Malik, S.: Challenges and solutions for late- And post-silicon design. IEEE Design and Test of Computers 25(4), 296-302 (2008). DOI http://dx.doi.org/10.1109/MDT.2008.91. URL http://dx.doi.org/10.1109/MDT. 2008.91.
2. Corporation, N.: NVIDIA Whitepaper: NVIDIA's Next Generation CUDA Compute Architecture: Fermi. http://www.nvidia.com/content/PDF/fermi-white-papers/ NVIDIA-Fermi-Compute-Architecture-Whitepaper.pdf (2009).
3. Lindholm, E., Nickolls, J., Oberman, S., Montrym, J.: NVIDIA Tesla: A Unified Graphics and Computing Architecture. IEEE Micro 28, 39-55 (2008).
4. Seiler, L., Carmean, D., Sprangle, E., Forsyth, T., Abrash, M., Dubey, P., Junkins, S., Lake, A., Sugerman, J., Cavin, R., Espasa, R., Grochowski, E., Juan, T., Hanrahan, P.: Larrabee: A Many-Core x86 Architecture for Visual Computing. ACM Transactions on Graphics 27(3), 1-15 (2008). DOI http://doi.acm.org/10.1145/1360612.1360617.
5. Pham, D., Aipperspach, T., Boerstler, D., Bolliger, M., Chaudhry, R., Cox, D., Harvey, P., Harvey, P., Hofstee, H., Johns, C., et al.: Overview of the Architecture, Circuit Design, and Physical Implementation of a First-Generation Cell Processor. IEEE Journal of Solid-State Circuits 41(1), 179-196 (2006).
6. Hannig, F., Dutta, H., Teich, J.: Mapping a Class of Dependence Algorithms to Coarsegrained Reconfigurable Arrays: Architectural Parameters and Methodology. International Journal of Embedded Systems 2(1/2), 114-127 (2006).
7. Kissler, D., Hannig, F., Kupriyanov, A., Teich, J.: A Highly Parameterizable Parallel Processor Array Architecture. In: Proceedings of the IEEE International Conference on Field Programmable Technology (FPT), pp. 105-112. Bangkok, Thailand (2006).
8. Vangal, S., Howard, J., Ruhl, G., Dighe, S., Wilson, H., Tschanz, J., Finan, D., Iyer, P., Singh, A., Jacob, T., et al.: An 80-Tile 1.28 TFLOPS Network-on-Chip in 65nm CMOS. In: SolidState Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, pp. 98-589 (2007).
9. Feautrier, P.: Automatic Parallelization in the Polytope Model. Tech. Rep. 8, Laboratoire PRiSM, Université des Versailles St-Quentin en Yvelines, 45, avenue des États-Unis, F- 78035 Versailles Cedex (1996).
10. Hannig, F., Teich, J.: Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals. In: Proceedings of the 15th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), pp. 17-27. Galveston, TX, USA (2004).
11. Thomas, A., Becker, J.: New adaptive multi-grained hardware architecture for processing of dynamic function patterns. it - Information Technology 49(3), 165-173 (2007).
12. Teich, J.: Invasive Algorithms and Architectures. it - Information Technology 50(5), 300-310 (2008).
13. Cybenko, G.: Dynamic load balancing for distributed memory multiprocessors. Journal of Parallel and Distributed Computing 7, 279-301 (1989).
14. Boillat, J.E.: Load balancing and poisson equation in a graph. Concurrency: Practice and Experience 2, 289-313 (1990).
15. Rabani, Y., Sinclair, A., Wanka, R.: Local divergence of Markov chains and the analysis of iterative load-balancing schemes. In: Proc. 39th IEEE Symposium on Foundations of Computer Science (FOCS), pp. 694-703 (1998).
16. Sanders, P.: Randomized priority queues for fast parallel access. Journal Parallel and Distributed Computing, Special Issue on Parallel and Distributed Data Structures 49, 86-97 (1998).
17. Sanders, P.: Asynchronous scheduling of redundant disk arrays. IEEE Transactions on Computers 52(9), 1170-1184 (2003).
18. Short version in 12th ACM Symposium on Parallel Algorithms and Architectures, pages 89-98, 2000.
19. Charles, P., Grothoff, C., Saraswat, V., Donawa, C., Kielsstra, A., Ebcioglu, K., von Praun, C., Sarkar, V.: X10: An object-oriented approach to non-uniform cluster computing. In: Proceedings of the 20th annual ACM SIGPLAN conference on Object-oriented programming, systems, languages, and applications, pp. 519-538. ACM (2005).