Towards robust nano-CMOS sense amplifier design: A dual-threshold versus dual-oxide perspective

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2011, Pages 145-150

  Okobiah, Oghenekarho ^a   Mohanty, Saraju P ^a   Kougianos, Elias ^a   Poolakkaparambil, Mahesh ^b  

^a UNIVERSITY OF NORTH TEXAS   (United States)

^b OXFORD BROOKES UNIVERSITY   (United Kingdom)

Author keywords

DRAM; Nano cmos; Process variation; Sense amplifier

Indexed keywords

CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC LOSSES; LEAKAGE CURRENTS; PARAMETRIC AMPLIFIERS; THRESHOLD VOLTAGE;

DUAL OXIDE THICKNESS; DUAL THRESHOLD VOLTAGE; FIGURES OF MERITS; NANO CMOS; PARAMETRIC STUDY; PROCESS VARIATION; SENSE AMPLIFIER; STATISTICAL STUDY;

INTEGRATED CIRCUIT DESIGN;

EID: 79957701178     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1973009.1973039     Document Type: Conference Paper

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