Sense amplifier signal margins and process sensitivities

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 49, Issue 3, 2002, Pages 269-275

  Laurent, Duane G ^a,b  

^a IEEE   (United States)

^b STMICROELECTRONICS   (Italy)

Author keywords

DRAM; Refresh time; Sense amplifier; Signal margin

Indexed keywords

REFRESH TIME; SENSE AMPLIFIER; SENSE-TIME METHOD; SIGNAL MARGINS;

CMOS INTEGRATED CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; EXTRAPOLATION; STATISTICAL METHODS; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

AMPLIFIERS (ELECTRONIC);

EID: 0036505228     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.989159     Document Type: Article

References (8)

1. Optimized sensing scheme of DRAMs
2. Analysis and reduction of sense-amplifier offset
3. A circuit design to suppress asymmetrical characteristics in high-density DRAM sense amplifiers
4. Trends in megabit DRAM circuit design
5. Mismatch sensitivity of a simultaneously latched CMOS sense amplifier
6. Matching properties of MOS transistors
7. Design techniques for high-speed high-resolution comparators