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Volumn , Issue , 2011, Pages 291-301

Bus access design for combined worst and average case execution time optimization of predictable real-time applications on multiprocessor systems-on-chip

Author keywords

[No Author keywords available]

Indexed keywords

AVERAGE CASE; EXECUTION TIME; MULTIPROCESSOR SYSTEMS ON CHIPS; OPTIMIZATION TECHNIQUES; REAL-TIME APPLICATION; WORST CASE; WORST-CASE EXECUTION TIME;

EID: 79957597853     PISSN: 10801812     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTAS.2011.35     Document Type: Conference Paper
Times cited : (7)

References (17)
  • 1
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    • AEthereal Network on Chip: Concepts, Architectures, and Implementations
    • K. Goossens, J. Dielissen, and A. Radulescu, "AEthereal Network on Chip: Concepts, Architectures, and Implementations," IEEE Design & Test of Computers, vol. 2/3, pp. 115-127, 2005.
    • (2005) IEEE Design & Test of Computers , vol.2-3 , pp. 115-127
    • Goossens, K.1    Dielissen, J.2    Radulescu, A.3
  • 3
    • 0013225410 scopus 로고    scopus 로고
    • A Review of Worst-Case Execution-Time Analysis
    • P. Puschner and A. Burns, "A Review of Worst-Case Execution-Time Analysis," Real-Time Systems, vol. 2/3, pp. 115-127, 2000.
    • (2000) Real-Time Systems , vol.2-3 , pp. 115-127
    • Puschner, P.1    Burns, A.2
  • 4
    • 6944226720 scopus 로고    scopus 로고
    • Design for Timing Predictability
    • L. Thiele and R. Wilhelm, "Design for Timing Predictability," Real-Time Systems, vol. 28, no. 2/3, pp. 157-177, 2004.
    • (2004) Real-Time Systems , vol.28 , Issue.2-3 , pp. 157-177
    • Thiele, L.1    Wilhelm, R.2
  • 5
    • 63349086729 scopus 로고    scopus 로고
    • Providing Accurate Event Models for the Analysis of Heterogeneous Multiprocessor Systems
    • S. Schliecker, J. Rox, M. Ivers, and R. Ernst, "Providing Accurate Event Models for the Analysis of Heterogeneous Multiprocessor Systems," in CODES+ISSS, 2008.
    • CODES+ISSS, 2008
    • Schliecker, S.1    Rox, J.2    Ivers, M.3    Ernst, R.4
  • 7
    • 70350738621 scopus 로고    scopus 로고
    • WCET-aware Register Allocation based on Graph Coloring
    • H. Falk, "WCET-aware Register Allocation based on Graph Coloring," in DAC, 2009.
    • (2009) DAC
    • Falk, H.1
  • 8
    • 34547224257 scopus 로고    scopus 로고
    • A multiprocessor systems-on-chip for real-time biomedical monitoring and analysis: Architectural design space exploration
    • I. A. Khatib, D. Bertozzi, F. Poletti, L. Benini, et al., "A multiprocessor systems-on-chip for real-time biomedical monitoring and analysis: Architectural design space exploration," in DAC, 2006, pp. 125-131.
    • (2006) DAC , pp. 125-131
    • Khatib, I.A.1    Bertozzi, D.2    Poletti, F.3    Benini, L.4
  • 11
    • 0036294704 scopus 로고    scopus 로고
    • Overview of bus-based system-on-chip interconnections
    • E. Salminen, V. Lahtinen, K. Kuusilinna, and T. Hamalainen, "Overview of bus-based system-on-chip interconnections," in ISCAS, 2002, pp. 372-375.
    • (2002) ISCAS , pp. 372-375
    • Salminen, E.1    Lahtinen, V.2    Kuusilinna, K.3    Hamalainen, T.4
  • 14
    • 0015482117 scopus 로고
    • Optimal Scheduling for two processor systems
    • E. C. Jr and R. Graham, "Optimal Scheduling for two processor systems," Acta Informatica, vol. 1, pp. 200-213, 1972.
    • (1972) Acta Informatica , vol.1 , pp. 200-213
    • Graham Jr., E.C.R.1
  • 17
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    • homepage
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    • MPARM


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.