Efficient processor support for DRFx, a memory model with exceptions

International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Volumn , Issue , 2011, Pages 53-65

  Singh, Abhayendra ^a   Marino, Daniel ^b   Narayanasamy, Satish ^a   Millstein, Todd ^b   Musuvathi, Madanlal ^c  

^a UNIVERSITY OF MICHIGAN   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c MICROSOFT RESEARCH   (United States)

Author keywords

Data races; Memory model exception; Memory models; Soft fences

Indexed keywords

DATA-RACES; EFFICIENT IMPLEMENTATION; HARDWARE OPTIMIZATION; HARDWARE SIMULATORS; JAVA MEMORY MODEL; MEMORY MODEL EXCEPTION; MEMORY MODELS; MICRO-ARCHITECTURE DESIGN; SHARED MEMORIES; SOFT FENCES;

ARCHITECTURE; COMPUTER SOFTWARE; DESIGN; FENCES; HIGH LEVEL LANGUAGES; JAVA PROGRAMMING LANGUAGE; OPTIMIZATION; SEMANTICS;

PROGRAM COMPILERS;

EID: 79953102527     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1950365.1950375     Document Type: Conference Paper

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