Foundations of the C++ concurrency memory model

Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI)

Volumn , Issue , 2008, Pages 68-78

  Boehm, Hans J ^a   Adve, Sarita V ^b  

^a HEWLETT PACKARD LABORATORIES   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

C++; Data race; Memory consistency; Memory model; Sequential consistency; Trylock

Indexed keywords

ADA (PROGRAMMING LANGUAGE); C (PROGRAMMING LANGUAGE); COMPUTER SOFTWARE; COMPUTERS; CONCURRENCY CONTROL; INFORMATION THEORY; JAVA PROGRAMMING LANGUAGE; LINGUISTICS; QUERY LANGUAGES; SEMANTICS;

C++; DATA RACE; MEMORY CONSISTENCY; MEMORY MODEL; SEQUENTIAL CONSISTENCY; TRYLOCK;

COMPUTER PROGRAMMING LANGUAGES;

EID: 57349165412     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1375581.1375591     Document Type: Conference Paper

References (33)

1. S. V. Adve. Designing Memory Consistency Models for Shared-Memory Multiprocessors. PhD thesis, University of Wisconsin-Madison, 1993.
2. S. V. Adve and K. Gharachorloo. Shared memory consistency models: A tutorial. IEEE Computer, 29(12): 66-76, 1996.
3. S. V. Adve and M. D. Hill. Weak ordering-A new definition. In Proc. 17th Intl. Symp. Computer Architecture, pages 2-14, 1990.
4. AMD Corp. AMD64 Architecture Programmer's Manual - Volume 2: System Programming, July 2007.
5. D. Aspinall and J. Sevcik. Java memory model examples: Good, bad, and ugly. VAMP07 Proceedings http://www.cs.ru.nl/̃chaack/VAMP07/,2007.
6. H. Boehm and N. Maclaren. Should volatile acquire atomicity and thread visibility semantics? C++ standards committee paper WG21/N2016 = J16/06-0086, http://www.open-std.org/JTC1/SC22/WG21/docs/papers/2007/n2016.html, April 2006.
7. H.-J. Boehm. Threads cannot be implemented as a library. In Proc. Conf. on Programming Language Design and Implementation, 2005.
8. H.-J. Boehm. A less formal explanation of the proposed C++ concurrency memory model. C++ standards committee paper WG21/N2480 = J16/07-350, http://www.open-std.org/JTC1/SC22/WG21/docs/papers/2007/n2480.html, December 2007.
9. H.-J. Boehm. Memory model rationales. C++ standards committee paper WG21/N2176 = J16/07-0036, http://www.open-std. org/JTC1/SC22/WG21/docs/papers/ 2007/n2176.htm1, March 2007.
10. H.-J. Boehm. N2338: Concurrency memory model compiler consequences. C++ standards committee paper WG21/N2338=J16/07-198, http://www.open-std.org/JTC1/ SC22/WG21/docs/papers/ 2007/n2338.htm, August 2007.
11. H.-J. Boehm. N2392: A memory model for C++: Sequential consistency for race-free programs. C++ standards committee paper WG21/N2392=J16/07-252, http://www.open-std.org/JTC1/SC22/WG21/docs/papers/2007/n2392.htm, September 2007.
12. H.-J. Boehm. Reordering constraints for pthread-style locks. In Proc. 12th Symp. Principles and Practice of Parallel Programming, pages 173-182, 2007.
13. H.-J. Boehm and L. Crowl. C++ atomic types and operations. C++ standards committee paper WG21/N2427=J16/07-0297, http: //www.open-std.org/JTC1/SC22/WG21/ docs/papers/2007/n2427.htm, October 2007.
14. C++ Standards Committee, Pete Becker, ed. Working Draft, Standard for Programming Language C++. C++ standards committee paper WG21/N2461=J16/07-0331, http://www.open-std.org/JTC1/SC22/WG21/docs/papers/2007/n2461.pdf, October 2007.
15. L. Ceze et al. Bulk SC: Bulk Enforcement of Sequential Consistency. In Proc. Intl. Symp. on Computer Architecture, 2007.
16. T. Elmas, S. Qadeer, and S. Tasiran. A race and transaction-aware Java runtime. In Proc. Conf. on Programming Language Design and Implementation, pages 245-255, 2007.
17. K. Gharachorloo. Memory Consistency Models for Shared Memory Multiprocessors. PhD thesis, Stanford University, 1995.
18. K. Gharachorloo et al. Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors. In Proc. 17th Intl. Symp. on Computer Architecture, pages 15-26, 1990.
19. K. Gharachorloo, A. Gupta, and J. Hennessy. Two Techniques to Enhance the Performance of Memory Consistency Models. In Proc. Intl. Conf. on Parallel Processing, pages 1355-1364, 1991.
20. W. H. Harrison. Compiler analysis of the value ranges for variables. IEEE Trans. Software Engineering, 3(3), May 1977.
21. IEEE and The Open Group. IEEE Standard 1003.1-2001. IEEE, 2001.
22. Intel Corp. Intel 64 Architecture Memory Ordering White Paper, August 2007. http://www.intel.com/products/procesEor/manuals/318147.pdf.
23. A. Kamil, J. Su, and K. Yelick. Making sequential consistency practical in titanium. In Proceedings of the 2005 ACM/IEEE SC-05 Conference (SC'05), page November, 2005.
24. L. Lamport. How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Transactions on Computers, C-28(9): 690-691, 1979.
25. J. Manson, W. Pugh, and S. Adve. The Java memory model. In Proc. Symp. on Principles of Programming Languages, 2005.
26. S. Narayanasamy et al. Automatically classifying benign and harmful data races using replay analysis. In Proc. Conf. on Programming Language Design and Implementation, pages 22-31, 2007.
27. C. Nelson and H.-J. Boehm. Concurrency memory model (final revision). C++ standards committee paper WG21/N2429=J16/07-0299, http://www.open-std.org/JTC1/ SC22/WG21/docs/papers/2007/n2429.htm, October 2007.
28. P. Ranganathan, V. S. Pai, and S. V. Adve. Using Speculative Retirement and Larger Instruction Windows to Narrow the Performance Gap between Memory Consistency Models. In Proc. Symposium on Parallel Algorithms and Architectures, 1997.
29. D. Shasha and M. Snir. Efficient and correct execution of parallel programs that share memory. ACM Transactions on Programming Languages and Systems, 10(2): 282-312, April 1988.
30. Z. Sura et al. Compiler Techniques for High Performance Sequentially Consistent Java Programs. In Symp. Principles and Practice of Parallel Programming, 2005.
31. H. Sutter. Prism: A principle-based sequential memory model for microsoft native code platforms. C++ standards committee paper WG21/N2197 = J16/07-0057, http://www.open-std.org/JTC1/SC22/WG21/docs/papers/2007/n2197.pdf, March 2007.
32. United States Department of Defense. Reference Manual for the Ada Programming Language: ANS1/MIL-STD-1815A-1983 Standard 1003.1-2001, 1983. Springer.
33. T. Wenisch et al. Mechanisms for Store-wait-free Multiprocessors. In Proc. Intl. Symp. on Computer Architecture, 2007.