Temperature-dependent modeling and characterization of through-silicon via capacitance

IEEE Electron Device Letters

Volumn 32, Issue 4, 2011, Pages 563-565

  Katti, Guruprasad ^a,b   Stucchi, Michele ^a   Velenis, Dimitrios ^a   Soŕee, Bart ^a,c   De Meyer, Kristin ^a,b   Dehaene, Wim ^a,b  

^a IMEC   (Belgium)

^b Katholieke Universiteit Leuven   (Belgium)

^c UNIVERSITY OF ANTWERP   (Belgium)

Author keywords

Temperature; three dimensional integrated circuits (3 D ICs); through silicon via (TSV); TSV capacitance

Indexed keywords

DOPED SUBSTRATES; EFFECT OF TEMPERATURE; ELECTRICAL MEASUREMENT; OPERATING TEMPERATURE; OXIDE THICKNESS; SEMI-ANALYTICAL MODEL; TECHNOLOGY PARAMETERS; TEMPERATURE DEPENDENT; TEMPERATURE RISE; THREE DIMENSIONAL INTEGRATED CIRCUITS; THROUGH-SILICON VIA (TSV); TSV CAPACITANCE;

INTEGRATED CIRCUITS; TEMPERATURE; THREE DIMENSIONAL;

CAPACITANCE;

EID: 79953057449     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2011.2109052     Document Type: Article

References (11)

1. K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, "3D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration," Proc. IEEE, vol. 89, no. 5, pp. 602-633, May 2001.
2. A. W. Topol, D. C. La Tulipe, Jr., L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, and M. Ieong, "Three-dimensional integrated circuits," IBM J. Res. Develop., vol. 50, no. 4/5, pp. 491-506, Jul.-Sep. 2006. (Pubitemid 44364166)
3. G. Katti, A. Mercha, J. Van Olmen, C. Huyghebaert, A. Jourdain, M. Stucchi, M. Rakowski, I. Debusschere, P. Soussan, W. Dehaene, K. De Meyer, Y. Travaly, E. Beyne, S. Biesemans, and B. Swinnen, "3D stacked ICs using Cu TSVs and die to wafer hybrid collective bonding," in IEDM Tech. Dig., 2009, pp. 357-360.
4. H. Kikuchi, Y. Yamada, A. Ali, J. Liang, T. Fukushima, T. Tanaka, and M. Koyanagi, "Tungsten through-silicon via technology for threedimensionalLSIs," Jpn. J. Appl.Phys., vol. 47, no. 4, pp. 2801-2806, 2008.
5. G. Katti, M. Stucchi, K. De Mayer, andW. Dehaene, "Electrical modeling & characterization of through silicon via (TSV) for 3D ICs," IEEE Trans. Electron Devices, vol. 57, no. 1, pp. 256-262, Jan. 2010.
6. C. Xu, H. Li, R. Suaya, and K. Banerjee, "Compact AC modeling and analysis of Cu, W, and CNT based through-silicon vias (TSVs) in 3-D ICs," in IEDM Tech. Dig., Dec. 2009, pp. 7-9.
7. T. Bandyopadhyay, R. Chatterjee, D. Chung, M. Swaminanithan, and R. Tummala, "Electrical modeling of through silicon and package vias," in Proc. IEEE Int. Conf. 3D Syst. Integr., Sep. 2009, pp. 28-30.
8. G. Katti, A. Mercha, M. Stucchi, Z. Tokei, D. Velenis, J. Van Olmen, C. Huyghebaert, A. Jourdain, M. Rakowski, I. Debusschere, P. Soussan, H. Oprins, W. Dehaene, K. De Meyer, Y. Travaly, E. Beyne, S. Biesemans, and B. Swinnen, "Temperature dependent electrical characteristics of through-Si-via (TSV) interconnections," in Proc. IITC, 2010, pp. 1-3.
9. A. B. Sproul and M. A. Green, "Improved value for the silicon intrinsic carrier concentration from 275 to 300 K," J. Appl. Phys., vol. 70, no. 2, pp. 846-854, Jul. 1991.
10. W. Baomin, R. Guoping, J. Yulong, Q. Xinping, L. Bingzong, and L. Ran, "Capacitance-voltage characterization of fully silicided gated MOS capacitor," J. Semicond., vol. 30, no. 3, p. 034 002, Mar. 2009.
11. G. Katti, M. Stucchi, J. Van Olmen, K. De Meyer, and W. Dehaene, "Through-silicon-via capacitance reduction technique to benefit 3-D IC performance," IEEE Electron Device Lett., vol. 31, no. 6, pp. 549-551, Jun. 2010.