Gate-all-around junctionless transistors with heavily doped polysilicon nanowire channels

IEEE Electron Device Letters

Volumn 32, Issue 4, 2011, Pages 521-523

  Su, Chun Jung ^a   Tsai, Tzu I ^a   Liou, Yu Ling ^a   Lin, Zer Ming ^a   Lin, Horng Chih ^a   Chao, Tien Sheng ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Accumulation mode; gate all around (GAA); inversion mode (IM); nanowire (NW); thin film transistor (TFT)

Indexed keywords

ACCUMULATION MODES; DOPING CONCENTRATION; DRAIN REGION; FABRICATION PROCESS; GATE ALL AROUND (GAA); GATE-ALL-AROUND; HEAVILY DOPED; IN-SITU; INVERSION MODES; MATERIAL FEATURES; NANOWIRE TRANSISTORS; ON/OFF CURRENT RATIO; POLY-SI; POLYCRYSTALLINE SILICON (POLY-SI); SOURCE/DRAIN SERIES RESISTANCES; SYSTEM ON PANEL; THIN-FILM TRANSISTOR (TFT);

ELECTRIC RESISTANCE; GALLIUM ALLOYS; NANOWIRES; POLYSILICON; SEMICONDUCTOR DOPING;

THIN FILM TRANSISTORS;

EID: 79953039939     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2011.2107498     Document Type: Article

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