Post-manufacturing, 17-times acceptable raw bit error rate enhancement, dynamic codeword transition ECC scheme for highly reliable solid-state drives, SSDs

Solid-State Electronics

Volumn 58, Issue 1, 2011, Pages 2-10

  Tanakamaru, Shuhei ^a   Fukuda, Mayumi ^a   Higuchi, Kazuhide ^a   Esumi, Atsushi ^b   Ito, Mitsuyoshi ^b   Li, Kai ^b   Takeuchi, Ken ^a  

^a UNIVERSITY OF TOKYO   (Japan)

^b SIGLEAD Inc   (Japan)

Author keywords

ECC; Error correcting code; NAND Flash memory; Solid state drive; SSD

Indexed keywords

BEST-EFFORT; BIT-ERRORS; CHANNEL INTERLEAVING; CODEWORD; COST PENALTY; DUAL CHANNEL; ECC; ECC SCHEME; ERROR CORRECTING CODE; FAILURE RATE; HIGH-SPEED MEMORY; LOWER-POWER CONSUMPTION; MOBILE PHONE APPLICATIONS; MP-3 PLAYERS; NAND FLASH MEMORY; PARITY BITS; READ PERFORMANCE; RELIABLE OPERATION; SSD; STILL CAMERAS; USER DATA;

DRIVES; FLASH MEMORY; HARD DISK STORAGE; MANUFACTURE; NAND CIRCUITS; TELECOMMUNICATION EQUIPMENT;

BIT ERROR RATE;

EID: 79952283183     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2010.11.025     Document Type: Conference Paper

References (15)

1. T. Tanzawa, T. Tanaka, K. Takeuchi, R. Shirota, S. Aritome, and H. Watanabe IEEE J Solid-State Circ 32 1997 662 669
2. Micheloni R, Ravasio R, Marelli A, Alice E, Altieri V, Bovino A, et al. IEEE int solid-state circuits conf dig tech pap; 2006. p. 497-8.
3. Tanakamaru S, Esumi A, Ito M, Li K, Takeuchi K. IEEE int memory workshop; 2010. p. 88-91.
4. MacKay DJC. Information theory, inference, and learning algorithms, Cambridge; 2003.
5. Micheloni R, Marelli A, Ravasio R. Error correction codes for non-volatile memories. Springer; 2008.
6. S. Gregori, A. Cabrini, O. Khouri, and G. Torelli Proc IEEE 91 2003 602 616
7. Chen Y, Parhi KK. IEEE int conference on acoustics, speech and signal processing proceedings; 2004. p. 73-6.
8. Kim H, Park JH, Park KT, Kwak P, Kwon O, Kim C, et al. IEEE int solid-state circuits conf dig tech pap; 2010. p. 442-43.
9. Marotta GG, Macerola A, D'Alessandro A, Torsi A, Cerafogli C, Lattaro C, et al. IEEE int solid-state circuits conf dig tech pap; 2010. p. 444-5.
10. Lee C, Lee SK, Ahn S, Lee J, Park W, Cho Y, et al. IEEE int solid-state circuits conf dig tech pap; 2010. p. 446-7.
11. J.D. Lee, S.H. Hur, and J.D. Choi IEEE Electron Dev Lett 23 2002 264 266
12. Ichige M, Takeuchi Y, Sugimae K, Sato A, Matsui M, Kamiguchi T, et al. IEEE symposium on VLSI tech dig tech pap; 2003. p. 89-90.
13. Inoh K. IEEE symposium on VLSI technology, short course; 2007.
14. Kurata H, Otsuga K, Kotabe A, Kajiyama S, Osabe T, Sasago Y, et al. IEEE symposium on VLSI circuits dig tech pap; 2006. p. 112-3.
15. N. Mielke, T. Marquart, N. Wu, J. Kessenich, H. Belgal, and E. Schares IEEE Int Reliab Phys Symp 9-19 2008