A 159mm2 32nm 32Gb MLC NAND-flash memory with 200MB/s asynchronous DDR interface

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 442-443

  Kim, Hyunggon ^a   Park, Jung Hoon ^a   Park, Ki Tae ^a   Kwak, Pansuk ^a   Kwon, Ohsuk ^a   Kim, Chulbum ^a   Lee, Younyeol ^a   Park, Sangsoo ^a   Kim, Kyungmin ^a   Cho, Doohyun ^a   Lee, Juseok ^a   Song, Jungho ^a   Lee, Soowoong ^a   Yoo, Hyukjun ^a   Kim, Sanglok ^a   Yu, Seungwoo ^a   Kim, Sungjun ^a   Lee, Sungsoo ^a   Kyung, Kyehyun ^a   Lim, Yong Ho ^a   Chung, Chilhee ^a   more..

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

32 NM TECHNOLOGY; CHIP SIZES; DEVICE-SCALING; DOUBLE DATA RATE; EMERGING MARKETS; FLASH CARD; FUNDAMENTAL FEATURES; HIGH-SPEED DATA; LOW COSTS; MULTILEVEL CELL; NAND FLASH; NAND FLASH MEMORY; PAGE SIZES; PERFORMANCE DEGRADATION; SIGNAL BUS; SPEED INTERFACES; STORAGE CAPACITY;

MICROPROCESSOR CHIPS;

FLASH MEMORY;

EID: 77952212747     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433912     Document Type: Conference Paper

References (8)

1. D. Nobunaga, et al., "A 50nm 8Gb NAND Flash Memory with 100MB/s Program Throughput and 200MB/s DDR Interface", ISSCC Dig. Tech. Papers, pp. 426-427, Feb., 2008.
2. K.-T. Park et al., "A 64-cell NAND Flash Memory with Asymmetric S/D Structure for Sub-40nm Technology and Beyond", Dig. Symp. VLSI Technology, pp. 19-20, Jun. 2006.
3. K.-T. Park et al., "Scalable Wordline Shielding Scheme using Dummy Cell beyond 40nm NAND Flash Memory for Eliminating Abnormal Disturb of Edge Memory Cell", Ext. Abst. Of SSDM, pp. 298-299, Sep. 2006.
4. T. Cho et al., "A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512Mb single-level modes", IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1700-1706, Nov. 2001.
5. K.-T. Park et al., "A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories", IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 919-928, Nov. 2008.
6. K.-D. Suh et al., "A 3.3V 32Mb NAND flash memory with incremental step pulse programming scheme", IEEE J. Solid-State Circuits, vol. 30, no. 11, pp. 1149-1156, Nov. 1995.
7. R. Cernea, et al., "A 34MB/s-Program-Throughput 16Gb MLC NAND with All-Bitline Architrecture in 56nm", ISSCC Dig. Tech. Papers, pp. 420-421, Feb., 2008.
8. K. Takeuchi et al., "A multipage cell architecture for high-speed programming multilevel NAND flash memories", IEEE J. Solid-State Circuits, vol. 33, no. 8, pp. 1228-1238, Aug. 1998.