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Volumn , Issue , 2010, Pages 331-334

Choice of power and control hardware for smart LED luminary

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY EFFICIENCY; LIGHTING; LIGHTING FIXTURES; SENSORS;

EID: 79952154368     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/BEC.2010.5630783     Document Type: Conference Paper
Times cited : (16)

References (19)
  • 1
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    • (1998) Proc. IEEE , vol.86 , pp. 664-686
    • Mazumder, P.1
  • 5
    • 10944263163 scopus 로고    scopus 로고
    • Improved Vertically Stacked Si/SiGe Resonant Interband Tunnel Diode Pair with Small Peak Voltage Shift and Unequal Peak Currents
    • N. C. Jin, R. Yu, P.R. Berger, P. E. Thompson, "Improved Vertically Stacked Si/SiGe Resonant Interband Tunnel Diode Pair with Small Peak Voltage Shift and Unequal Peak Currents", Electron. Lett., vol. 40, pp. 1548-1550, 2004.
    • (2004) Electron. Lett. , vol.40 , pp. 1548-1550
    • Jin, J.C.1    Yu., R.2    Berger, P.R.3    Thompson, P.E.4
  • 6
    • 33646246724 scopus 로고    scopus 로고
    • Si/SiGe resonant interband tunnel diode with fro 20.2 GHz and peak current density 218 kA/cm2for K-band mixed-signal applications
    • S.-Y.Y. Chung, R. Jin, N. Park, S-Y. Berger, P.E. Thompson, "Si/SiGe resonant interband tunnel diode with fro 20.2 GHz and peak current density 218 kA/cm2for K-band mixed-signal applications", IEEE Electron Device Lett., vol. 27, no. 5, pp. 364-367, 2006.
    • (2006) IEEE Electron Device Lett , vol.27 , Issue.5 , pp. 364-367
    • Chung, S.-Y.Y.1    Jin, R.2    Park, N.3    Berger, S.Y.4    Thompson, P.E.5
  • 8
    • 70350586433 scopus 로고    scopus 로고
    • Si/SiGe Resonant Interband Tunneling Diodes Incorporating δ- Doping Layers Grown by Chemical Vapor Deposition
    • S.-Y. Park, R. Anisha, P. R. Berger, R. Loo, N. D. Nguyen, S. Takeuchi, M. Caymax, "Si/SiGe Resonant Interband Tunneling Diodes Incorporating δ- Doping Layers Grown by Chemical Vapor Deposition", IEEE Electron Devices Letters, vol. 30, no. 11, pp. 1173-1175, Nov. 2009.
    • (2009) IEEE Electron Devices Letters , vol.30 , Issue.11 , pp. 1173-1175
    • Park, S.-Y.1    Anisha, R.2    Berger, P.R.3    Loo, R.4    Nguyen, N.D.5    Takeuchi, S.6    Caymax, M.7
  • 9
    • 64549164463 scopus 로고    scopus 로고
    • Record PVCR GaAs-based tunnel diodes fabricated on Si substrates using aspect ratio trapping
    • S.L. Rommel et al., "Record PVCR GaAs-based tunnel diodes fabricated on Si substrates using aspect ratio trapping", IEEE International Electron Devices Meeting (IEDM), 2008.
    • (2008) IEEE International Electron Devices Meeting (IEDM)
    • Rommel, S.L.1
  • 16
    • 0034289973 scopus 로고    scopus 로고
    • Threshold logic circuit design of parallel adders using resonant tunnelling devices
    • C. Pacha et al., "Threshold logic circuit design of parallel adders using resonant tunnelling devices", IEEE Trans. VLSI Systems, vol. 8, no. 5, pp. 558-572, 2000.
    • (2000) IEEE Trans. VLSI Systems , vol.8 , Issue.5 , pp. 558-572
    • Pacha, C.1
  • 17
    • 33751546627 scopus 로고    scopus 로고
    • Single phase clock scheme for MOBILE logic gates
    • H. Pettenghi et al., "Single phase clock scheme for MOBILE logic gates", Electronics Letters, vol. 42, no. 24, pp. 1382-1383, Nov. 2006.
    • (2006) Electronics Letters , vol.42 , Issue.24 , pp. 1382-1383
    • Pettenghi, H.1
  • 18
    • 0024611252 scopus 로고
    • High-speed CMOS circuit technique
    • J. Yuan, C. Svensson, "High-speed CMOS circuit technique", IEEE J Solid-State Circuits, vol. 24, pp. 62-70, Feb. 1989.
    • (1989) IEEE J Solid-State Circuits , vol.24 , pp. 62-70
    • Yuan, J.1    Svensson, C.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.