-
1
-
-
0000900676
-
Digital circuit applications of resonant tunnelling devices
-
P. Mazumder et al., "Digital circuit applications of resonant tunnelling devices", Proc. IEEE, vol. 86, pp. 664-686, Apr. 1998.
-
(1998)
Proc. IEEE
, vol.86
, pp. 664-686
-
-
Mazumder, P.1
-
2
-
-
33847157864
-
100 GHz Operation of a Resonant Tunneling Logic Gate MOBILE Having a Symmetric Configuration
-
K.S. Maezawa, H. Kishimoto, T. Mizutani, "100 GHz Operation of a Resonant Tunneling Logic Gate MOBILE Having a Symmetric Configuration", Proc. Int. Canf on Indium Phosphide and Related Materials, pp. 46-49, 2006.
-
(2006)
Proc. Int. Canf on Indium Phosphide and Related Materials
, pp. 46-49
-
-
Maezawa, K.S.1
Kishimoto, H.2
Mizutani, T.3
-
4
-
-
18044383521
-
Overgrown Si/SiGe Resonant Interband Tunnel Diodes for Integration with CMOS
-
S. V. Sudirgo, R. Nandgaonkar, R.P. Hirschman, S. Rommel, S. K. Kurinec, P.E. Thompson, J. Niu, P.R. Berger, "Overgrown Si/SiGe Resonant Interband Tunnel Diodes for Integration with CMOS", 62nd Device Research Conf. Dig., vol. 1, pp. 109-110, 2004.
-
(2004)
62nd Device Research Conf. Dig
, vol.1
, pp. 109-110
-
-
Sudirgo, S.V.1
Nandgaonkar, R.2
Hirschman, R.P.3
Rommel, S.4
Kurinec, S.K.5
Thompson, P.E.6
Niu, J.7
Berger, P.R.8
-
5
-
-
10944263163
-
Improved Vertically Stacked Si/SiGe Resonant Interband Tunnel Diode Pair with Small Peak Voltage Shift and Unequal Peak Currents
-
N. C. Jin, R. Yu, P.R. Berger, P. E. Thompson, "Improved Vertically Stacked Si/SiGe Resonant Interband Tunnel Diode Pair with Small Peak Voltage Shift and Unequal Peak Currents", Electron. Lett., vol. 40, pp. 1548-1550, 2004.
-
(2004)
Electron. Lett.
, vol.40
, pp. 1548-1550
-
-
Jin, J.C.1
Yu., R.2
Berger, P.R.3
Thompson, P.E.4
-
6
-
-
33646246724
-
Si/SiGe resonant interband tunnel diode with fro 20.2 GHz and peak current density 218 kA/cm2for K-band mixed-signal applications
-
S.-Y.Y. Chung, R. Jin, N. Park, S-Y. Berger, P.E. Thompson, "Si/SiGe resonant interband tunnel diode with fro 20.2 GHz and peak current density 218 kA/cm2for K-band mixed-signal applications", IEEE Electron Device Lett., vol. 27, no. 5, pp. 364-367, 2006.
-
(2006)
IEEE Electron Device Lett
, vol.27
, Issue.5
, pp. 364-367
-
-
Chung, S.-Y.Y.1
Jin, R.2
Park, N.3
Berger, S.Y.4
Thompson, P.E.5
-
7
-
-
67650290350
-
P and B doped Si Resonant Interband Tunnel Diodes with as-grown Negative Differential Resistance
-
P.E. Thompson, G.G. Jernigan, S.-Y. Park, R. Yu, R. Anisha, P.R. Berger, D. Pawlik, R. Krom, S.L. Rommel, "P and B doped Si Resonant Interband Tunnel Diodes with as-grown Negative Differential Resistance", Electronics Letters, vol. 45, no. 14, pp. 759-761, 2009.
-
(2009)
Electronics Letters
, vol.45
, Issue.14
, pp. 759-761
-
-
Thompson, P.E.1
Jernigan, G.G.2
Park, S.-Y.3
Yu, R.4
Anisha, R.5
Anisha, R.6
Berger, P.R.7
Pawlik, D.8
Krom, R.9
Rommel, S.L.10
-
8
-
-
70350586433
-
Si/SiGe Resonant Interband Tunneling Diodes Incorporating δ- Doping Layers Grown by Chemical Vapor Deposition
-
S.-Y. Park, R. Anisha, P. R. Berger, R. Loo, N. D. Nguyen, S. Takeuchi, M. Caymax, "Si/SiGe Resonant Interband Tunneling Diodes Incorporating δ- Doping Layers Grown by Chemical Vapor Deposition", IEEE Electron Devices Letters, vol. 30, no. 11, pp. 1173-1175, Nov. 2009.
-
(2009)
IEEE Electron Devices Letters
, vol.30
, Issue.11
, pp. 1173-1175
-
-
Park, S.-Y.1
Anisha, R.2
Berger, P.R.3
Loo, R.4
Nguyen, N.D.5
Takeuchi, S.6
Caymax, M.7
-
9
-
-
64549164463
-
Record PVCR GaAs-based tunnel diodes fabricated on Si substrates using aspect ratio trapping
-
S.L. Rommel et al., "Record PVCR GaAs-based tunnel diodes fabricated on Si substrates using aspect ratio trapping", IEEE International Electron Devices Meeting (IEDM), 2008.
-
(2008)
IEEE International Electron Devices Meeting (IEDM)
-
-
Rommel, S.L.1
-
10
-
-
47549112287
-
Alloyed Junction Ge Esaki Diodes on Si Substrates realised by Aspect Ratio Trapping Technique
-
D. Pawlik, S. Sieg, S.K. Kurinec, S.L. Rommel, Z. Cheng, J.-S. Park, J. Hydrick, A. Lochtefeld, "Alloyed Junction Ge Esaki Diodes on Si Substrates realised by Aspect Ratio Trapping Technique", Electronics Letters, vol. 44, no. 15, pp. 930-931, July 2008.
-
(2008)
Electronics Letters
, vol.44
, Issue.15
, pp. 930-931
-
-
Pawlik, D.1
Sieg, S.2
Kurinec, S.K.3
Rommel, S.L.4
Cheng, Z.5
Park, J.-S.6
Hydrick, J.7
Lochtefeld, A.8
-
11
-
-
4544274990
-
On Circuit Techniques to Improve Noise Immunity of CMOS Dynamic Logic
-
L. Ding, Pinaki Mazumder, "On Circuit Techniques to Improve Noise Immunity of CMOS Dynamic Logic", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 9, pp. 919-925, Sept. 2004.
-
(2004)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, vol.12
, Issue.9
, pp. 919-925
-
-
Ding Pinaki Mazumder, L.1
Pinaki Mazumder2
-
12
-
-
77950334732
-
One-Transistor Bistable-Body Tunnel SRAM
-
K. Karda, J. Brockman, S. Sutar, A. Seabaugh, J. Nahas, "One-Transistor Bistable-Body Tunnel SRAM", IEEE International Conference on IC Design and Tecnology ICICDT'09, pp. 233-236, 2009.
-
(2009)
IEEE International Conference on IC Design and Tecnology ICICDT'09
, pp. 233-236
-
-
Karda, K.1
Brockman, J.2
Sutar, S.3
Seabaugh, A.4
Nahas, J.5
-
16
-
-
0034289973
-
Threshold logic circuit design of parallel adders using resonant tunnelling devices
-
C. Pacha et al., "Threshold logic circuit design of parallel adders using resonant tunnelling devices", IEEE Trans. VLSI Systems, vol. 8, no. 5, pp. 558-572, 2000.
-
(2000)
IEEE Trans. VLSI Systems
, vol.8
, Issue.5
, pp. 558-572
-
-
Pacha, C.1
-
17
-
-
33751546627
-
Single phase clock scheme for MOBILE logic gates
-
H. Pettenghi et al., "Single phase clock scheme for MOBILE logic gates", Electronics Letters, vol. 42, no. 24, pp. 1382-1383, Nov. 2006.
-
(2006)
Electronics Letters
, vol.42
, Issue.24
, pp. 1382-1383
-
-
Pettenghi, H.1
-
18
-
-
0024611252
-
High-speed CMOS circuit technique
-
J. Yuan, C. Svensson, "High-speed CMOS circuit technique", IEEE J Solid-State Circuits, vol. 24, pp. 62-70, Feb. 1989.
-
(1989)
IEEE J Solid-State Circuits
, vol.24
, pp. 62-70
-
-
Yuan, J.1
Svensson, C.2
|