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Volumn , Issue , 2009, Pages 233-236

One-transistor bistable-body tunnel SRAM

Author keywords

SRAM; Static random access memory; TSRAM; Tunnel diode

Indexed keywords

BAND TO BAND TUNNELING; BI-STABILITY; BISTABLES; BODY VOLTAGE; MOS TRANSISTORS; MOS-FET; SRAM; SRAM CELL; STATIC RANDOM ACCESS MEMORY;

EID: 77950334732     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICDT.2009.5166303     Document Type: Conference Paper
Times cited : (10)

References (10)
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    • Y. Wang, U. Bhattacharya, F. Hamzaoglu, P. Kolar, Y. Ng, L. Wei, Y. Zhang, K. Zhang, and M. Bohr, "A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management," 2009 ISSCC, pp. 455-456.
    • 2009 ISSCC , pp. 455-456
    • Wang, Y.1    Bhattacharya, U.2    Hamzaoglu, F.3    Kolar, P.4    Ng, Y.5    Wei, L.6    Zhang, Y.7    Zhang, K.8    Bohr, M.9
  • 2
    • 0033116185 scopus 로고    scopus 로고
    • Tunneling-based SRAM
    • Apr.
    • J. van der Wagt, "Tunneling-based SRAM," Proc. IEEE, vol. 87, pp. 571-595, Apr. 1999
    • (1999) Proc. IEEE , vol.87 , pp. 571-595
    • Van Der Wagt, J.1
  • 4
    • 34247502116 scopus 로고    scopus 로고
    • Predictive technology model for nano-CMOS design exploration
    • Apr.
    • W. Zhao and Y. Cao, "Predictive technology model for nano-CMOS design exploration," ACM J. Emerging Technologies in Computing Systems, vol. 3, no.1, pp. 1-17, Apr. 2007.
    • (2007) ACM J. Emerging Technologies in Computing Systems , vol.3 , Issue.1 , pp. 1-17
    • Zhao, W.1    Cao, Y.2
  • 7
    • 0036857083 scopus 로고    scopus 로고
    • Memory design using a one-transistor gain cell on SOI
    • November
    • T. Ohsawa et al., "Memory design using a one-transistor gain cell on SOI," IEEE Journal of Solid-State Circuits, Vol. 37, No.11, pp. 1510-1522, November 2002.
    • (2002) IEEE Journal of Solid-State Circuits , vol.37 , Issue.11 , pp. 1510-1522
    • Ohsawa, T.1
  • 8
    • 46049103027 scopus 로고    scopus 로고
    • Floating body cell with independently-controlled double gates for high density memory
    • I. Ban , U. E. Avci , U. Shah , C. E. Barns , D. L. Kencke and P. Chang "Floating body cell with independently-controlled double gates for high density memory," IEDM Tech. Dig., 2006.
    • (2006) IEDM Tech. Dig.
    • Ban, I.1    Avci, U.E.2    Shah, U.3    Barns, C.E.4    Kencke, D.L.5    Chang, P.6
  • 9
    • 77950310598 scopus 로고    scopus 로고
    • 0.3As quantum well transistor on silicon substrate using thin (<= 2 um) composite buffer architecture for high-speed and low-voltage (0.5 V) logic applications
    • 0.3As quantum well transistor on silicon substrate using thin (<= 2 um) composite buffer architecture for high-speed and low-voltage (0.5 V) logic applications," IEDM Tech. Dig. (2008) pp. 4.
    • (2008) IEDM Tech. Dig. , pp. 4
    • Hudait, M.K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.